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2008-01-05For each channel, tell if it is single-ended or differential if we can knowMiod Vallat
this. Might help before someone sets his disks on fire. Especially with boards where not all channels are of the same type.
2008-01-03Enable wide transfers in the IOPB on wide busses, and get the IOPB passthroughMiod Vallat
SCSI commands length correct (it's a length in 16 bit words, not in 8 bit bytes).
2008-01-02Do not invalidate the 88410 cache without flushing it first; this isMiod Vallat
probably due either to an error in the cpu-to-88410 communication protocol, or to a bug in the '410 (but since I do not know how to get its revision, I can't tell whether this is the obscure v1 bug or not). This allows osiop-connected devices to work correctly on 197SP/DP boards.
2008-01-01Match on Cougar boards, and try to drive them like Jaguars on steroids. OnMiod Vallat
wide Cougars, use one command queue per target and disable lun support, so that we do not overflow the board's memory; and since we are behaving as a Jaguar, do not do tagged queuing or synchronous transfer negotiation. Tested on two MVME328XT-2 (4220 and second revision artwork 4220) narrow Cougar-I (but wide external connectors), but probes fail with select timeout so far; I could not get various Motorola BUG to probe devices on these boards either, so we're even (and maybe both my boards are toast, but I won't bet money on this).
2008-01-01A potpourri of bugfixes:Miod Vallat
- switch back to a fixed queue number allocation, but keep the rotating command queue entries. Force openings to 1 because of this. - make sure to mark the queue as ready before invoking scsi_done(), which could trigger a request for the same target. - allocate a command queue and an IOPB at the same time, instead of using two routines and ugly queue pointer arithmetic. This makes the daughterboard work, as long as the first scsi chain is not empty.
2007-12-31replace ctob/btoc by ptoa/atop as done for other architecturesMartin Reindl
2007-12-27Remove leftover code in m197_machdep.c, back when I wanted to address theMiod Vallat
DCAM2 boards in a different way.
2007-12-27Make the mvme188 interrupt handling closer to the aviion interrupt handling:Miod Vallat
non-VME syscon interrupt sources will now use their own intrhand array, and interrupt sources will be enabled in the arbiter as interrupt handlers are registered. This allows VME devices to use the whole 256 interrupts range.
2007-12-26Since no cache flush/inval operation will occur before we enable D$, andMiod Vallat
we never disable it, it is not necessary to check for D$ to be enabled before acting. That's a few more cycles spared.
2007-12-26Remove the last debug bit from the PSR on 88110: do not force memory accessesMiod Vallat
instructions to be serialized (this defeats the purpose of having a superscalar processor, and accesses to volatile variables are done with explicit memory barriers anyway). This brings a HUGE speedup: openssl speed -elapsed shows AES is 90% faster, blowfish is 75% faster, and sha1 is 50% faster. Not so bad! However, doing this increases the pressure on the processor bus, so it is necessary to increase the processor bus timeout on 40MHz boards again (to 256 usec). ``black cat'' 50MHz boards seem to be unaffected, so they remain at 64 usec.
2007-12-25Limit physmem to 32MB on 01-W3869B02[EF] boards which shipped with 64MB ofMiod Vallat
memory but a memory controller limited to 32MB. Not tested for lack of such crippled hardware, just the average once-per-leap-year act of niceness from me (a bit early though).
2007-12-25Tell 197SP and 197DP apart in MULTIPROCESSOR kernels.Miod Vallat
2007-12-25Increase timeout on the processor bus when running without snooping enabled.Miod Vallat
This lets 40MHz MVME197LE boards run with instruction cache enabled, and also fixes random instruction faults occuring on the early 50MHz models.
2007-12-22Move initial PSR initialization to a separate routine, instead of duplicatingMiod Vallat
it five times.
2007-12-22Enable branch prediction on MC88110 revision 5 and later, since we canMiod Vallat
workaround errata #1 differently on these models.
2007-12-21Change the EF_xxx constants to be real offsets within the trapframe, insteadMiod Vallat
of offsets / sizeof(register_t), and nuke the REG_OFF macro. No functional change.
2007-12-20Do not wait for the end of the universe if delay(0).Miod Vallat
2007-12-20Stricter range checks in mmap function.Miod Vallat
2007-12-15Get the MVME197 memory size from the BusSwitch decoders.Miod Vallat
2007-12-15Unconditionnaly disable the instruction cache on 40MHz MVME197LE boards,Miod Vallat
so that they run stably. Definitely overkill and causing a severe performance hit (they now run about as fast as a 25MHz board with I$ enabled would), but sometimes you can't fight silicon bugs. Other boards (i.e. 50MHz ones) are not affected.
2007-12-15All MVME BUG manuals concur on SR3 being the only register needing to beMiod Vallat
preserved across BUG calls, but on the other hand the last 16 traps need to be restored to BUG values, not only trap #496.
2007-12-15Since the 88110 can not invalidate a particular tlb entry, do not stackMiod Vallat
invalidate tlb ipis, and turn them into simple ``handle once'' ipis.
2007-12-15Move the cmmu lock back from 8820x-specific code to global, and use it onMiod Vallat
MVME197DP to serialize 88410 operations.
2007-12-13Disable write posting, this does not work on BusSwitch revision #1. The BUGMiod Vallat
should do this for us, but better play safe.
2007-12-09I honestly do not remember what 88110 errata convinced me to disableMiod Vallat
out-of-order (superscalar) execution on these processors. Since OoO brings a nice 50% to 250% speedup (as shown by ``openssl speed''), it is definitely worth enabling.
2007-12-09Nuke evil common, spotted by martin@Miod Vallat
2007-12-08Better siginfo fault codes for floating point exceptions on 88110, withMiod Vallat
more work in progress to handle these exceptions correctly, and document a new undocumented and evil chip bug while there.
2007-12-05Make the CPU_88100 and CPU_88110 constants match the architectural numberMiod Vallat
field from the processor identification register; this allows .S code which needs to decide on the cpu type at runtime to check quicker, without needing to access memory. No functional change.
2007-12-05Correctly setup the seconday processor on 197DP, and get it ready to acceptMiod Vallat
IPIs.
2007-12-04Work in progress SMP code for 88110 processor using the BusSwitch chip asMiod Vallat
an IPI facility, for MVME197DP. It's still missing a few remote cache IPIs and IPI do not seem to be reliably triggered on remote processors at the moment (but this could be a problem on the board I am currently testing on), at least it will boot multiuser using only cpu0 to schedule processes.
2007-12-04Correctly set the stack pointer of a secondary processor to the endMiod Vallat
of its initialization stack. Oops.
2007-12-04Better cache routines for 88410, will only flush in pages instead ofMiod Vallat
flushing the whole secondary cache. This does not work around the snooping errata yet, I'm trying to get something not too ugly first.
2007-12-04Program the abort interrupt source correctly.Miod Vallat
2007-12-02Rework mmu initialization so that we do not actually enable translationMiod Vallat
until cmmu_set_sapr(). Also, do not enable snooping on MVME197LE, so that we don't have to add workarounds for snooping problems later.
2007-12-02Add a workaround for the MVME197LE reset issue when not system controller.Miod Vallat
2007-12-02Remove 88110 control registers accessors which are never used anywhere.Miod Vallat
2007-12-02The beginning of a real floating-point exception handler for the 88110. TheMiod Vallat
existing code to enable TCFP was broken, as it was not setting the TCFP bit in the right register. So far, the exception handler will deliver SIGFPE in all cases. It will eventually do the necessary rounding, and handle the odd-numbered register pair operation, as I get time to write this (or see how much can be lifted from the 88100 floating-point exception code).
2007-12-02Do not pass UPAGES and USPACE (under the name USIZE) in assym.h, code whichMiod Vallat
needs it includes <machine/param.h> already.
2007-12-02Better inline assembler constructs.Miod Vallat
2007-12-02Rework the __mp_lock code to not spin at spllock(), kinda similar to theMiod Vallat
x86 __mp_lock changes, but keeping the internal __cpu_simplelock_t to guarantee atomic access to the __mp_lock fields.
2007-11-30Define NORMAL_C_NOP everywhere.Miod Vallat
2007-11-27typos; ok jmc@Martynas Venckus
sys/dev/pci/pciide.c from naddy@
2007-11-26Move the implementation of __mp_lock (biglock) into machine dependentArtur Grabowski
code. At this moment all architectures get the copy of the old code except i386 which gets a new shiny implementation that doesn't spin at splhigh (doh!) and doesn't try to grab the biglock when releasing the biglock (double doh!). Shaves 10% of system time during kernel compile and might solve a few bugs as a bonus. Other architectures coming shortly. miod@ deraadt@ ok
2007-11-26few more dribbles of LIBKERN cleanupTheo de Raadt
2007-11-26More LIBKERN bits that go awayTheo de Raadt
2007-11-25libkern, begone. Move to a new mechanism where config(8)'s "file"Theo de Raadt
directive can select between MI and MD versions of these files. At the same time, adjust the boot programs to pick exactly what they need, instead of the 7 or 8 mechanisms previously used. There will be some fallout from this, but testing it all by myself is a ridiculously slow process; it will be finished in-tree. Various developers were very nice and avoided making fun of me when I was gibbering in the corner..
2007-11-25Get rid of the kernel 'libcompat' framework, and instead use conf/files toTheo de Raadt
decide which files must be pulled into the kernel. Also conditionalize the pulling of those files based on the COMPAT_* options.
2007-11-24Fix a stupid underscore bug in memory area computations in the cache functions,Miod Vallat
it's amazing things didn't break.
2007-11-24Be sure to program the busswitch interrupt selection register on 197SPMiod Vallat
and 197DP to route interrupts to the processor we're booting on. This allows a 197DP to run when booting from the second cpu.
2007-11-22Split the cmmu code routines into single 88110 (MVME197LE) and 88110+88410Miod Vallat
combos (MVME197SP/DP), and implement supposedly smarter cache routines. There is still room for improvement, however, cache flush operation errata permissing. Tested on 197LE and 197DP.
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