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path: root/sys/arch/octeon/include
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2017-07-13Add handling for the third interrupt summary vector,Visa Hankala
needed by upcoming work.
2017-07-03Attach com(4) using fdt on octeon.Visa Hankala
The relevant part of uartbus(4) is made part of the com(4) glue to avoid extra maneuvers in the code.
2017-06-19Fix the timecounter register on CN72xx/CN73xx.Visa Hankala
2017-06-19There is no RTC on the E1000 board.Visa Hankala
2017-06-18Split octeon interrupt code into a glue layer and a CIU driver.Visa Hankala
This makes possible to add drivers for other interrupt controllers on the platform. The glue layer has been derived from arm64/armv7.
2017-06-18Drop unnecessary call to octeon_setintrmask(). The function gets calledVisa Hankala
by the splx() handler.
2017-06-11Define register_splx_handler() in one place.Visa Hankala
2017-05-08add a BUS_DMA_64BIT flag to bus_dma on all our archs.David Gwynne
this is so drivers can advertise that they can handle 64 dma addresses to the platform. it may choose to handle dmamaps differently based on this flag. tweaks and ok tom@ ok kettenis@
2017-04-07Add prid for CN72xx/CN73xx.Visa Hankala
2017-04-07Make SoC version available in a simple form.Visa Hankala
2017-04-06Extend the fdt interrupt API a little.Visa Hankala
2017-02-26Define cache line size for the per-cpu API.Visa Hankala
2016-12-17Fix IO clock speed and system reset on Octeon III.Visa Hankala
2016-12-17There is no RTC on Shasta, so do not attach the driver.Visa Hankala
2016-12-08Add a routine for setting up interrupt handlers using fdt.Visa Hankala
ok kettenis@
2016-12-08Add fdt_attach_args and simplebus for implementing fdt-capableVisa Hankala
drivers on octeon. Adapted from armv7. ok kettenis@
2016-10-29Make PHY address lookups fail instead of using CAM-0100 entriesVisa Hankala
when the system board is unhandled.
2016-07-16Add $OpenBSD$ / replace $Id$ with $OpenBSD$.Visa Hankala
2016-07-16Remove octeon_disable_interrupt() and octeon_restore_status().Visa Hankala
They are unused and equivalent to disableintr() and setsr(). While here, clean up a few other leftovers.
2016-07-10Use the synciobdma instruction instead of the sync instruction forVisa Hankala
flushing any pending local IOBDMA operations. The sync instruction is overkill because it implies a full memory barrier. ok jasper@ (long time ago)
2016-07-05Add openprom(4) for octeon.Visa Hankala
ok kettenis@ deraadt@ jasper@
2016-07-01Add fdt init for octeon.Visa Hankala
2016-06-22Add support for the second GMX interface on Octeon II. This enablesVisa Hankala
ports eth[0-3] on 8-port EdgeRouters. Currently, port eth0 maps to network interface cnmac4, eth1 to cnmac5 etc. ok dlg@, tested by martijn@
2016-05-30Fill the packet data pool with standard mbuf clusters instead ofVisa Hankala
driver-specific memory blocks. This lets the cnmac(4) RX path run without an mbuf ext_free callback. ok uebayasi@
2016-05-24Reduce the size of gather buffers and allocate more of them to makeVisa Hankala
better use of memory. This should prevent gather buffer starvation on currently supported systems. Discussed with mpi@
2016-05-04Initial support for MSI-X. Only supported on amd64 for now. I have diffs toMark Kettenis
actually use this in em(4) and xhci(4), but I'm not committing those yet because we almost certainly need to save and restore the MSI-X registers during suspend/resume. However, this allows mpi@ to play with multiple-vector support in networking hardware. Requested by mpi@ ok mlarkin@, mikeb@
2016-03-21On Octeon systems, U-Boot provides a list of usable memory regions. UseVisa Hankala
the list instead of hardcoded regions in memory setup. Works on EdgeRouter Lite, EdgeRouter Pro, Lanner MR326b and Movidis 16x. Tested by jj@ Tested by and ok jmatthew@
2016-03-06Rename mips64's trap_frame into trapframe.Martin Pieuchot
For coherency with other archs and in order to use it in MI code. ok visa@, tobiasu@
2016-01-05Some implementations of HitSyncDCache() call pmap_extract() for va->paVisa Hankala
conversion. Because pmap_extract() acquires the PTE mutex, a "locking against myself" panic is triggered if the cache routine gets called in a context where the mutex is already held. In the pmap, all calls to HitSyncDCache() are for a whole page. Add a new cache routine, HitSyncDCachePage(), which gets both the va and the pa of a page. This removes the need of the va->pa conversion. The new routine has the same signature as SyncDCachePage(), allowing reuse of the same routine for cache implementations that do not need differences between "Hit" and non-"Hit" routines. With the diff, POWER Indigo2 R8000 boots multiuser again. Tested on sgi GENERIC-IP27.MP and octeon GENERIC.MP, too. Diff from miod@, ok kettenis@
2015-09-30Use #ifndef _MACHINE_DISKLABEL_H_ everywhere. Replace _ARM_DISKLABEL_H_Kenneth R Westerback
and _SH_DISKLABEL_H_ with _MACHINE_DISKLABEL_H_. Add the guard to loongson and octeon. The #defines are not used anywhere else in the tree so no functional change.
2015-09-30Use consistant whitespace/comments for #define'ing LABELSECTOR,Kenneth R Westerback
LABELOFFSET and MAXPARTITIONS. Easier on the eye when scanning through all these files. No functional change.
2015-09-26Let MP-safe interrupt handlers run without the kernel lock on octeon.Visa Hankala
ok kettenis@
2015-09-13intr_barrier(9) for loongson, octeon and sgi.Mark Kettenis
2015-09-09The mplock implementations on MP-enabled mips64 platforms, octeon andVisa Hankala
sgi, are identical. Put one implementation in mips64 and drop the platform-specific copies, to remove duplicated code. ok miod@
2015-07-20Add a new flash driver for Octeon that allows access to the internalPaul Irofti
memory on (at least) D-Link DSR500 machines. This follows the CFI specification with code borrowed from zrouter (FreeBSD). The idea, once the current driver is thoroughly tested, would be to move it to MI land. The prerequisites to MI are width, shift and row detection and handling. In the long run I hope to be able to also add wdc support. For now write support is disabled. Okay miod@, deraadt@.
2015-07-17Remove {LOAD,COUNT}_TEXTA from libsa loadfile, it only made sense for a.outMiod Vallat
kernels and we no longer have any.
2015-07-15Ditch the octeon simulator non-sense.Paul Irofti
Discussed with miod@.
2015-07-08unify the mutex implementations on all the mips64 platforms.David Gwynne
this basically copies the sgi implementation to mips64 and removes it from the rest. this way they get an optimised UP mutex implementation and correct asserts on all platforms. ok miod@ jmatthew@
2014-10-26- add board type of edgerouter proJasper Lievisse Adriaanse
- don't attach octrtc on the edgerouter pro either openbsd boots fine on this system, but as there's no ethernet support yet there's no storage at all right now. ok pirofti@
2014-10-26define octeon model cn61xx pass 1.1Jasper Lievisse Adriaanse
ok pirofti@
2014-08-12Lower VM_PHYSSEG_MAX from the mips64 default to a generous 4, and changeMiod Vallat
allocation strategy to VM_PSTRAT_BIGFIRST.
2014-08-11Remove evcnt and %b format strings relying upon SEIL extensions. This givesMiod Vallat
OCTEON_ETH_DEBUG kernels a chance to build. No functional change for regular kernels.
2014-07-14whitespaceJasper Lievisse Adriaanse
2014-07-12add guards to just make available to the bootblocks what they need.Jasper Lievisse Adriaanse
prompted by miod@
2014-07-09Add ffs routine needed for upcoming octhci interrupt routine.Paul Irofti
Okay miod@
2014-06-17The io clock on Octeon II (CN6xxx) runs at a different rate to the cpu clock.Jonathan Matthew
Program the uarts based on the io clock rate on these platforms. ok jasper@ pirofti@ yasuoka@
2014-03-31Due the virtually indexed nature of the L1 instruction cache on most mipsMiod Vallat
processors, every time a new text page is mapped in a pmap, the L1 I$ is flushed for the va spanned by this page. Since we map pages of our binaries upon demand, as they get faulted in, but uvm_fault() tries to map the few neighbour pages, this can end up in a bunch of pmap_enter() calls in a row, for executable mappings. If the L1 I$ is small enough, this can cause the whole L1 I$ cache to be flushed several times. Change pmap_enter() to postpone these flushes by only registering the pending flushes, and have pmap_update() perform them. The cpu-specific cache code can then optimize this to avoid unnecessary operations. Tested on R4000SC, R4600SC, R5000SC, RM7000, R10000 with 4KB and 16KB page sizes (coherent and non-coherent designs), and Loongson 2F by mikeb@ and me. Should not affect anything on Octeon since there is no way to flush a subset of I$ anyway.
2014-03-29It's been a quarter century: we can assume volatile is present with that name.Philip Guenther
ok dlg@ mpi@ deraadt@
2014-03-10Support BUS_DMA_NOCACHE in bus_dma(9). Memory allocations done withMiod Vallat
BUS_DMA_NOCACHE (or BUS_DMA_COHERENT if the platform does not have coherent caches) will use PMAP_NOCACHE when invoking pmap_enter(), to avoid creating cached mappings, and then evicting them from the cache.
2014-03-09Rework the per-cpu cache information. Use a common struct to store the lineMiod Vallat
size, the number of sets, and the total size (and the set size, for convenience) per cache (I$, D$, L2, L3). This allows cpu.c to print the number of ways (sets) of L2 and L3 caches from the cache information, rather than hardcoding this from the processor type.
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