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path: root/sys/arch/riscv64/include
AgeCommit message (Expand)Author
2024-10-21define _MACHINE_ARCH not _MACHINE_ARCJonathan Gray
2024-10-16remove unneeded frame.h and riscvreg.h includesJonathan Gray
2024-10-15remove unneeded pte.h includeJonathan Gray
2024-10-14remove unneeded vmparam.h include from pte.hJonathan Gray
2024-10-14remove unneeded device.h includeJonathan Gray
2024-07-14Add elf_aux_info(3)Jeremie Courreges-Anglas
2024-06-11Enable UVM percpu cache on riscv64Jeremie Courreges-Anglas
2024-05-22remove prototypes with no matching function and externs with no varJonathan Gray
2024-04-29remove prototypes for removed functionsJonathan Gray
2024-04-06Now that we support RISC-V CPUs that have MMUs with memory cachabilityMark Kettenis
2024-03-29Use SBI calls to reboot or power down the machine when the firmwareMark Kettenis
2024-03-27The RISC-V architecture specification says that memory read/writes areMark Kettenis
2024-02-25clockintr: rename "struct clockintr_queue" to "struct clockqueue"Scott Soule Cheloha
2024-02-03Implement Multiple Message MSI support on arm64. As on amd64 this isMark Kettenis
2024-01-27On Allwinner D1, the SBI call to schedule timer interrupts doesn't work.Mark Kettenis
2024-01-24clockintr: switch from callee- to caller-allocated clockintr structsScott Soule Cheloha
2024-01-24Remove atomic_store_64(), misleading and now unusedJeremie Courreges-Anglas
2024-01-23T-Head implemented a page attribute extension that violates the RISC-VMark Kettenis
2023-12-14NKMEMPAGES_MAX_DEFAULT is no longer used. Remove it from param.h.Claudio Jeker
2023-12-13Implement per-CPU caching for the page table page (vp) pool and the PTEJeremie Courreges-Anglas
2023-12-11Implement per-CPU caching for the page table page (vp) pool and the PTEMark Kettenis
2023-11-28remove more unused definesJonathan Gray
2023-11-24Remove unused direct map defines and macros, originating from FreeBSD.Miod Vallat
2023-11-06Provide machine/apmvar.h on riscv64 tooJeremie Courreges-Anglas
2023-09-22move simplebusvar.h so it can be used without ifdefJonathan Gray
2023-09-19Import the DVFS code from arm64.Mark Kettenis
2023-08-23all platforms: separate cpu_initclocks() from cpu_startclock()Scott Soule Cheloha
2023-08-21Remove dead code.Miod Vallat
2023-08-05cpu_idle_{enter,leave} are no-ops on riscv64, so just #definePhilip Guenther
2023-07-25statclock: move profil(2), GPROF code to profclock(), gmonclock()Scott Soule Cheloha
2023-07-02all platforms, kernel: remove __HAVE_CLOCKINTR symbolScott Soule Cheloha
2023-03-19Aggressively randomize the location of the stack on all 64-bit architecturesMark Kettenis
2023-02-16Remove obsolete __HAVE_VM_PAGE_MD define - all platforms provide vm_page_mdMiod Vallat
2022-12-29Avoid doing cache flush/invalidate operations for DMA memory allocated withMark Kettenis
2022-12-06Drop unused WEAK_REFERENCE macroJeremie Courreges-Anglas
2022-12-03Add ENTRY_NB() and use it for brk.S and sbrk.S on riscv64Jeremie Courreges-Anglas
2022-12-02Drop _C_LABEL() uses in riscv64-specific codeJeremie Courreges-Anglas
2022-11-19riscv64: switch to clockintrScott Soule Cheloha
2022-08-30Remove long unused WARN_REFERENCES macro; idea guenther@, ok jsg@ jca@Miod Vallat
2022-08-29use ansi volatile keyword, not __volatileJonathan Gray
2022-08-09riscv64: trigger deferred timer interrupts from splx(9)Scott Soule Cheloha
2022-06-28Remove unused field d_poll from struct cdevsw.Visa Hankala
2022-06-10Implement CPU_BUSY_CYCLE() with the ZiHintPause extensionJeremie Courreges-Anglas
2022-05-30Add sfgpio(4), a driver for the GPIO controller found on theMark Kettenis
2022-03-22Change VM_MIN_ADDRESS to PAGE_SIZE to forbid mapping anything at virtualMiod Vallat
2022-03-22Do not pretend there exist MD code for byte swapping yet provide copiesMiod Vallat
2022-02-24Fix kernel stack alignment on riscv64Visa Hankala
2022-02-24Fix PIC_SYM() macro: it never needs to token paste, so it's notPhilip Guenther
2022-02-23unifdef __ELF__Jonathan Gray
2022-01-16remove "for all AArch64 platforms" from commentJonathan Gray