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path: root/sys/arch/riscv64/include
AgeCommit message (Expand)Author
2022-01-16remove "for all AArch64 platforms" from commentJonathan Gray
2022-01-01Remove unused function prototype.Mark Kettenis
2021-10-05cleanup conf.c, and bring in wd(4) supportTheo de Raadt
2021-09-14Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)Jeremie Courreges-Anglas
2021-09-03Don't pretend we support PT_STEP on this architecture.Jeremie Courreges-Anglas
2021-09-03Enable ptrace(2) support for PT_GETFPREGS/PT_SETFPREGSJeremie Courreges-Anglas
2021-08-30Remove typedef of db_addr_t; mpi converted the users of it to vaddr_t alreadyJasper Lievisse Adriaanse
2021-07-24riscv64 userland timecounter supportJeremie Courreges-Anglas
2021-07-24Implement a workaround for the SiFive FU740 CIP-1200 errata.Mark Kettenis
2021-07-11convert db_addr_t to vaddr_tJasper Lievisse Adriaanse
2021-07-06Shifts (<<) of more than 32 bits must be done on 64-bit values.Patrick Wildt
2021-07-02Cleanup early bootstrap code. This mostly realigns the code with theMark Kettenis
2021-07-02Run SBI calls to to get mvendorid/marchid/mimplid on the actual CPU we'reMark Kettenis
2021-06-30Simplify the way we track the FPU state, using powerpc64 as a model.Mark Kettenis
2021-06-29SMP support. Mostly works, but occasionally craps out during boot.Mark Kettenis
2021-06-27Using the MI mplock should be fine on riscv64.Mark Kettenis
2021-06-27Add Hart State Management functions. These will be needed to spin upMark Kettenis
2021-06-25add SIZE_MAX. ok kettenis@Matthieu Herrb
2021-06-25use weaker fences for riscv64 membarJonathan Gray
2021-06-17On OpenBSD _JBLEN is the number of slots (of type long) in jmp_buf.Mark Kettenis
2021-06-16don't define __HAVE_ACPI to unbreak radeondrm buildJonathan Gray
2021-06-15Increase MAXDSIZ to 16GB. ok kettenis@Matthieu Herrb
2021-06-14Use uint64_t instead of u_long for pcitag_t.Mark Kettenis
2021-06-14add PCITAG_NODE and PCITAG_OFFSETTheo de Raadt
2021-06-02kernel: introduce per-CPU panic(9) message bufferscheloha
2021-05-21reduce diff relative to other arch (arm64 seems most relevant here)Theo de Raadt
2021-05-21delete useless commentTheo de Raadt
2021-05-20Significant overhaul of the floating point save/restore code.Dale Rahn
2021-05-19Add PCI support.Mark Kettenis
2021-05-19Bring riscv64 intr.c code in sync with arm64. This brings us:Mark Kettenis
2021-05-18Remove the no-op instruction cache flush/wb/inv operations and replace themMark Kettenis
2021-05-16ansiJonathan Gray
2021-05-15pmap_fault_fixup() does not need "int user"Theo de Raadt
2021-05-13Use intr_enable()/int_disable()/intr_restore() instead ofMark Kettenis
2021-05-13change sig_atomic_t from long to int matching all the other archsJonathan Gray
2021-05-12Correct defines for fenv rounding modes and change fenv_t and fexcept_tJonathan Gray
2021-05-12add OpenBSD rcs idsJonathan Gray
2021-05-11more whitespace cleanupsTheo de Raadt
2021-05-11whitespace cleanupTheo de Raadt
2021-05-09fpu_valid_opcode() did not correctly handle 16 bit fp instructionsJonathan Gray
2021-05-09Change offsets to (N * 8) to reduce chance of register clobber and mistakes.Dale Rahn
2021-05-08kernel setjmp saves 14 registers, not 13. ddb continue now works.Theo de Raadt
2021-05-05The StarFive JH7100 SoC found on the BeagleV beta boards has most ofMark Kettenis
2021-05-05use fence iorw,iorw for bus_space_barrier()Jonathan Gray
2021-05-04The clock on RISC-V is architectural, so we really don't need theMark Kettenis
2021-05-03Use the EFI memory map (if available) to determine available physicalMark Kettenis
2021-04-30remove now unused elf.hJonathan Gray
2021-04-30reduce diff to current arm64Jonathan Gray
2021-04-30Fix line swap resulting in misplaced ',' causing build error.Dale Rahn
2021-04-29Clean up <machine/ieeefp.h> and make sure the rounding mode bits match theMark Kettenis
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