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path: root/sys/arch/riscv64
AgeCommit message (Collapse)Author
2022-01-02addres -> addressJonathan Gray
2022-01-02establush -> establishJonathan Gray
2022-01-01Remove unused function prototype.Mark Kettenis
2022-01-01Add missing locking to pmap_extract(9) and pmap_unwire(9).Mark Kettenis
ok patrick@, mpi@
2021-12-17Disable a few warning flags that were introduced and enabled by defaultPatrick Wildt
with LLVM 13.
2021-12-11remove unused variable to fix build with llvm 13; ok jca@Christian Weisgerber
2021-12-09We only have one syscall table: inline sysent/SYS_MAXSYSCALL andPhilip Guenther
SYS_syscall as the nosys() function into the MD syscall entry routines and the SYSCALL_DEBUG support. Adjust alpha's syscall check to match the other archs. Also, make sysent const to get it into .rodata. With that, 'struct emul' is unused: delete it and all its references ok millert@
2021-11-30enable uhid/fidoTheo de Raadt
from Ashton Fagg
2021-11-27stop building kernels with -Wno-uninitialized on clang archsJonathan Gray
this hides real problems that could be found at build time ok kettenis@ visa@, ok sashan@ on amd64/i386
2021-11-26avoid clang -Wsometimes-uninitialized warning when MULTIPROCESSOR is notJonathan Gray
defined feedback from millert@, ok kettenis@, mips64 diff from and ok visa@
2021-11-14Make sure efiboot is built with RELA/REL relocations and not RELR,Philip Guenther
as self_reloc.c only handles the former. ok deraadt@ kettenis@
2021-11-11Retire switch(4) it never really was production ready and the OpenFlowClaudio Jeker
API implemented is a deadend. OK akoshibe@ yasuoka@ deraadt@ kn@ patrick@ sthen@
2021-10-26Remove more occurences of O_RDONLY in our bootloaders.Patrick Wildt
"just do it" deraadt@
2021-10-06Change sendsig() interface so that the MD code does not need to accessClaudio Jeker
data from struct process anymore. This changes how siginfo and onstack are accessed and make sendsig() more MP friendly. With and OK semarie@ OK kettenis@
2021-10-05cleanup conf.c, and bring in wd(4) supportTheo de Raadt
ok kettenis
2021-09-14Cleanup some style issues and remove some unused code. In particular,Mark Kettenis
remove the half-finished code to support the SV48 MMU page table layout. Currently there is no hardware that supports that model and I don't expect any hardware that does support it to show up anytime soon. ok mlarkin@
2021-09-14Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)Jeremie Courreges-Anglas
Modelled after the arm implementation. The first consumer would be __builtin___clear_cache() in libcompiler_rt. Input from kettenis@ and deraadt@, ok kettenis@
2021-09-03Zap a chatty printfJeremie Courreges-Anglas
ok mlarkin@ kettenis@
2021-09-03Don't pretend we support PT_STEP on this architecture.Jeremie Courreges-Anglas
The RISC-V doesn't seem to provide hardware support for generic purpose single stepping, and we're not emulating single stepping for riscv64 like we do for alpha or mips64. Hiding PT_STEP makes it possible to run inferior processes with a wip ports/devel/gdb update. ok kettenis@
2021-09-03Enable ptrace(2) support for PT_GETFPREGS/PT_SETFPREGSJeremie Courreges-Anglas
The code is already there, it was unreachable because of this #if 0. ok kettenis@
2021-09-02add aq(4) to amd64 RAMDISK_CD and riscv64 RAMDISKMike Larkin
2021-09-02aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adaptersMike Larkin
Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This driver supports 1Gbps through 10Gbps modes of operation based on the hardware and media/switch capabilities. The initial code was ported from NetBSD, with jmatthew@ finishing up the Tx/Rx ring support and interrupt handler routine. The driver only supports devices using firmware V2. This diff enables aq(4) on riscv64 and amd64, the only platforms where I have tested the driver, but it likely works on other architectures as well.
2021-08-31Using suser() instead of doing it manually.Jan Klemkow
ok patrick@
2021-08-30Remove typedef of db_addr_t; mpi converted the users of it to vaddr_t alreadyJasper Lievisse Adriaanse
back in 2019. ok mpi@
2021-08-02Add memory barrier (data FENCE) before making the SBI call to issue aMark Kettenis
FENCE.I instruction on the remote harts. According to the RISC-V ISA documentation this is necessary to make remote harts observe earlier stores. Also issue the local FENCE.I first; this is what both FreeBSD and Linux does. Seems to fix at least some of the issue we've seen running GENERIC.MP on MP machines. ok jca@
2021-07-30Use inline function for SFENCE.VMA instruction. Fixes missing "memory"Mark Kettenis
clobber in the inline assembly.
2021-07-30Cleanup ptrace-related code; still untested.Mark Kettenis
2021-07-26Print a few more registers in dump_regs().Mark Kettenis
2021-07-25enable iwm(4)Jonathan Gray
from Ashton Fagg who tested on 9260
2021-07-25enable ix(4)Jonathan Gray
from Ashton Fagg who tested on 82599
2021-07-24riscv64 userland timecounter supportJeremie Courreges-Anglas
ok kettenis@
2021-07-24Implement a workaround for the SiFive FU740 CIP-1200 errata.Mark Kettenis
Remove the (incomplete) support for ASIDs. RISC-V hardware that implements ASIDs doesn't exist at this moment and the current code interferes with the errata workaround and other pmap improvements we're planning to make. ok drahn@, jca@, deraadt@
2021-07-23Use 8/4/1 bytes loads/stores for copyin/copyout/kcopyJeremie Courreges-Anglas
Only use multiple bytes operations on properly aligned addresses, as I have observed a 40x penalty for unaligned 8 bytes operations compared to equivalent 1-byte loops on this Sifive Unmatched. The speed gain is small but significant. Input & ok kettenis@
2021-07-12Add uaudio(4) and umidi(4). ok kettenis@, mlarkin@Matthieu Herrb
2021-07-11convert db_addr_t to vaddr_tJasper Lievisse Adriaanse
2021-07-10tweak indentation of conditional in db_validate_address().Jasper Lievisse Adriaanse
this also matches arm64 now/again.
2021-07-09use vaddr_t as type for frames as is commonly used elsewhere tooJasper Lievisse Adriaanse
ok kettenis@
2021-07-06Shifts (<<) of more than 32 bits must be done on 64-bit values.Patrick Wildt
Reported by some grumpy old cheese lover "looks reasonable" jsg@ ok kettenis@
2021-07-02Remove bogus comments.Mark Kettenis
2021-07-02Remove a few pointless comments.Mark Kettenis
2021-07-02Cleanup early bootstrap code. This mostly realigns the code with theMark Kettenis
FreeBSD code from which it was derived. In particular, it uses the same trick to switch page tables as FreeBSD, which is what we use to spin up the secondary CPUs already. This avoids having to install a temporary 1:1 mapping. ok mlarkin@
2021-07-02Only do TLB shootdown on CPUs where a pmap is active. Only make SBI callsMark Kettenis
that do a remote SFENCE.VMA or FENCE.I if the set of hart IDs isn't empty. This significantly speeds things up. ok jsg@
2021-07-02Run SBI calls to to get mvendorid/marchid/mimplid on the actual CPU we'reMark Kettenis
probing and decode mvendorid and marchid. ok mlarkin@, deraadt@, jsg@
2021-06-30Simplify the way we track the FPU state, using powerpc64 as a model.Mark Kettenis
The new code still uses the clean/dirty state that the hardware reports to optimize saving/restoring the FPU register, but no longer attempts to keep the FPU registers alive across a context switch. Fixes panics seen on MP kernels. ok drahn@
2021-06-30add missing call to sbi_remote_fence_i()Jonathan Gray
ok kettenis@
2021-06-30MULTIPTOCESSOR -> MULTIPROCESSORJonathan Gray
ok deraadt@
2021-06-29SMP support. Mostly works, but occasionally craps out during boot.Mark Kettenis
ok drahn@
2021-06-29delete pre-EFI boot kernel location scriptingTheo de Raadt
ok drahn
2021-06-29sync maxusers with other 64bits architectures. ok kettenis@, deraadt@.Matthieu Herrb
2021-06-29The way we boot OpenBSD, there is no need to play the hart lottery.Mark Kettenis
This is essentially a remnant of early RISC-V, which used the Berkely Boot Loader. Modern RISC-V firmware makes sure only one hart is enabled and offsers SBI calls to start the other harts.
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