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AgeCommit message (Expand)Author
2024-10-21define _MACHINE_ARCH not _MACHINE_ARCJonathan Gray
2024-10-17use <machine/asm.h> not "machine/asm.h", for consistencyJonathan Gray
2024-10-17remove unneeded includesJonathan Gray
2024-10-16remove unneeded frame.h and riscvreg.h includesJonathan Gray
2024-10-15remove unneeded pte.h includeJonathan Gray
2024-10-14remove unneeded vmparam.h include from pte.hJonathan Gray
2024-10-14remove unneeded device.h includeJonathan Gray
2024-09-20remove unneeded semicolons; checked by millert@Jonathan Gray
2024-09-04Fix some spelling.Marcus Glocker
2024-08-18don't need to put config_activate_children inside cfattach, becauseTheo de Raadt
2024-08-06The devicetree spec says in section 2.4:Mark Kettenis
2024-07-14Add elf_aux_info(3)Jeremie Courreges-Anglas
2024-06-30we don't need the NOBYFOUR space-savings option anymore, that codepathTheo de Raadt
2024-06-26return type on a dedicated line when declaring functionsJonathan Gray
2024-06-23If an ioctl(2) request isn't implemented we should return ENOTTY.Mark Kettenis
2024-06-23Fix previous commit; add missing labelMark Kettenis
2024-06-20Instead of allocating an arbitrary amount of extra space, let the EFIMark Kettenis
2024-06-17KNFMark Kettenis
2024-06-17When loading a device tree using the "mach dtb" command, give firmwareMark Kettenis
2024-06-11Enable UVM percpu cache on riscv64Jeremie Courreges-Anglas
2024-06-11Clamp CPU clock frequencies to [min, max] range when determining theMark Kettenis
2024-06-11remove drm prototypes duplicating those in sys/conf.hJonathan Gray
2024-05-22remove prototypes with no matching function and externs with no varJonathan Gray
2024-05-13remove prototypes with no matching functionJonathan Gray
2024-04-30remove commented DEBUG_TIMER for timer driver removed in 2021Jonathan Gray
2024-04-29remove prototypes for removed functionsJonathan Gray
2024-04-29remove unused pmap_vp_remove()Jonathan Gray
2024-04-19Fix typo in commentJeremie Courreges-Anglas
2024-04-07The RISC-V architecture has cache-coherent DMA... until it doesn't. ThisMark Kettenis
2024-04-06Now that we support RISC-V CPUs that have MMUs with memory cachabilityMark Kettenis
2024-03-31Enable rge(4).Mark Kettenis
2024-03-29Use SBI calls to reboot or power down the machine when the firmwareMark Kettenis
2024-03-27The RISC-V architecture specification says that memory read/writes areMark Kettenis
2024-03-26The devicetree standard allows for multiple /memory nodes, each withMark Kettenis
2024-03-26Implement support for the RISC-V UEFI Boot Protocol. This provides usMark Kettenis
2024-03-25Add missing SFENCE.VMA instructions after switching page tables duringMark Kettenis
2024-03-07Enable dwxe(4)Kevin Lo
2024-02-25clockintr: rename "struct clockintr_queue" to "struct clockqueue"Scott Soule Cheloha
2024-02-23ddb(4): db_read_bytes/db_write_bytes: change dst/src parameter to void*Scott Soule Cheloha
2024-02-21revert r1.35David Gwynne
2024-02-21handle /reserved-memory nodes from device trees on arm64.David Gwynne
2024-02-17Add JH7100 I2C clocks.Mark Kettenis
2024-02-03Implement Multiple Message MSI support on arm64. As on amd64 this isMark Kettenis
2024-02-02Enable sximmc(4)Mark Kettenis
2024-01-27Add a few drivers to support Allwinner D1.Mark Kettenis
2024-01-27On Allwinner D1, the SBI call to schedule timer interrupts doesn't work.Mark Kettenis
2024-01-26Recognize the T-Head PLIC implementation.Mark Kettenis
2024-01-26Implement T-Head cache management operations which are needed to handleMark Kettenis
2024-01-24clockintr: switch from callee- to caller-allocated clockintr structsScott Soule Cheloha
2024-01-24Remove atomic_store_64(), misleading and now unusedJeremie Courreges-Anglas
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