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Instead of previous implementation, we won't use physical cpuid to fetch curcpu().
This requires to implement IP27/35 SMP.
Implemented getcurcpu() and setcurcpu() for it, smp_malloc() renamed alloc_contiguous_pages() because now it only allocate by page.
ok miod@
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two distinct sets of routines: one for the ARCBios-compatible path used on
non-KL systems (such as O2 and Octane), and one for the KL system using
dksc() paths.
When trying to match a dksc() path, walk the KL configuration of the whole
system until the dksc controller is found; since the controller numbers are
not assigned sequentially and contiguously, the old code would not work on
complex systems (such as when booting from controller #6 when #3 to #5 are
unaffected).
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and routines to turn a KL console and a KL component structs, respectively,
into struct sgi_device_location for further device identification.
XXX Due to the way PCI devices are numbered on PIC buses, this code is tainted
XXX by knowledge about PIC widgets, to compensate. I have considered changing
XXX xbridge(4) to have our PCI device numbering match KL on PIC-connected
XXX devices, but I expect this to be even uglier. This is not settled yet.
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identify a given device by its physical connection, and add a lazy compare
routine. This will be used shortly.
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No functional change yet.
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fake ARCBios component structures associated to the KL configuration.
The ARCBios data tells us if the device is the output console, and the
KL component data tells us its node and widget numbers.
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allows processors with different cache sizes to be used.
Cache management routines now take a struct cpu_info * as first parameter.
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processor (instead of sys_config.cpu[]), and pass it in the attach_args
when attaching cpu devices.
This allows per-cpu information to be gathered late in the bootstrap process,
and not be limited by an arbitrary MAX_CPUS limit; this will suit IP27 and
IP35 systems better.
While there, use this information to make sure delay() uses the speed
information from the cpu it is invoked on.
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ok miod@
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when invoking the cache functions. The physical address is needed when
operating on physically-indexed caches, such as the L2 cache on Loongson
processors.
Preprocessor abuse makes sure that the physical address computation gets
compiled out when running on a kernel compiled for virtually-indexed
caches only, such as the sgi kernel.
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(i.e. IP27 and IP30 sgi kernels).
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context.S fixes allows these settings to work for kernels linked in CKSEG0.
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rather than <mips64/param.h>.
For now, kernels are kept at 4KB to give people some time to build 16KB
compatible binaries; this will change before the end of this release cycle.
Use of 16KB page size kernels yields a 18% speedup (which, offset by the
1.6% slowdown caused by the pmap changes, yields a 16.6% overall speedup).
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ok miod@
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for the platform we are running on (i.e. trying to boot e.g. bsd.IP32 on an
IP27 machine).
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It prevents deadlock with TLB shootdown and clock interrupt.
ok miod@
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Also few xheart modification for SMP.
ok miod@
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struct intrhand, instead of having it malloc()'ed.
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address as a kernel variable for use by libkvm.
On sgi IP27 and IP30 kernels, use XKSEG instead of CKSSEG; this will allow
kernel KVM size to grow in the future if necessary.
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ok miod@
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as the onboard ioc device, if one has already been found on this node.
Also, on Origin 300, do not attempt to attach the PS/2 controller on the
onboard ioc(4) since PS/2 ports are not wired.
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system type list (which really is the system family) and a subsystem type.
No functional change yet.
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ok miod@
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to prevent further abuse of it.
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a frame and clock interrupt doesn't need a struct intrhand.
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specified in the kernel configuration file, but is provided by macebus(4)
as part of the child device attachment args, and provide both crime and
mace interrupt bitmasks; this allows us to only really enable interrupt
sources we care about, and to avoid invoking interrupt handler we don't need
to for the few mace interrupts multiplexed at the crime level.
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logical IPL level, and per-platform (IP27/IP30/IP32) code will from the
necessary hardware mask registers.
This allows the use of more than one interrupt mask register. Also, the
generic (platform independent) interrupt code shrinks a lot, and the actual
interrupt handler chains and masking information is now per-platform private
data.
Interrupt dispatching is generated from a template; more routines will be
added to the template to reduce platform-specific changes and share as much
code as possible.
Tested on IP27, IP30, IP32 and IP35.
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does almost exactly what splx() is doing if ipending is zero, and triggers
soft interrupts as well.
So don't bother checking for ipending in splx, and always invoke pending_int,
which gets renamed as splx_handler for consistency.
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coprocessor 0 sr level might come back in the future if hardware support
requires it, but at the moment it's getting in the way of larger changes.
``In the Attic, noone can hear you scream''
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in the coprocessor 0 status register (coupled with ICR on rm7k/rm9k), and
may be completely alien to real hardware interrupt masks, so don't make
things unnecessary confusing.
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on all systems but O2 (to catch up soon). Also use the IOC4 MCR register to
figure out the IOC4 clock, instead of checking the widget control register,
to be consistent with iof(4).
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long. Prompted by deraadt@ long ago.
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foo bricks (they differ by having PCI-X bridges instead of PCI bridges
but are otherwise built the same)
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OK miod@
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OK miod@
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needed for gcc -ftrampoline operation as well as by some third-party
software.
Although the implementation uses the sysarch() sysctl, the wrapper is
added to libc as it was a direct system call (which it is on IRIX).
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cpu_info pointer array, cpu_info iterator, cpu_number() implementation added.
constraint modifier fixed in lock.h to output correct assembly.
calling proc_trampoline_mp in exception.S.
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Tested by myself, sthen, oga, kettenis, and jasper.
Input from sthen and jasper.
ok kettenis
(Manpage follows shortly.)
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provide and use BUS_SPACE_BARRIER_xxx.
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bus_space_alloc() as a bitmask of flags, and not a boolean controlling
cacheability; and make sure the three MI BUS_SPACE_MAP_xxx values documented
in the manual page are defined on all platforms as well.
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