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path: root/sys/arch/sgi/xbow
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2011-04-17On IP27 systems, fill the array of node hub widget numbers early, so that allMiod Vallat
hubs are known during autoconf. Then, pick the most populated 2GB window as our DMA memory window. xbridge(4) can thus program the correct settings regardless of the order in which the xbow(4) attach.
2011-04-05Rename a few xbow global variable names to make them less ambiguous.Miod Vallat
Remember the hub widget number of each node, instead of only the master node. Use this in xbridge to compute the proper direct DMA map configuration register value (it needs to embed the hub widget number matching the physical address range). This should allow us to pick memory from a different node than the one we booted from, as the DMA window, if wanted.
2011-04-05Get rid of the ATE code, and do not assume the direct DMA window is set upMiod Vallat
at physical address zero onwards, but instead assume it is controlled by the dma_constraints range. This will eventually allow a different window to be selected.
2011-03-13Disable write gathering on devio settings we inherit from ARCS.Miod Vallat
2010-12-04Introduce a new pci routine, pci_conf_size(), which returns the size of aMiod Vallat
given pcitag_t configuration address space. Currently, all pci controllers will return the usual 0x100 bytes of PCI configuration space, but this will eventually change on PCIe-capable controlers. ok kettenis@
2010-11-27Missed one rbus_new_body() call in previous change.Miod Vallat
2010-09-22remove unused offset argument to rbus functionsJonathan Gray
ok krw@ kettenis@
2010-09-20Get rid of evcount's support for arranging counters in a treeMatthew Dempsky
hierarchy. Everything attached to a single root node anyway, so at best we had a bush. "i think it is good" deraadt@
2010-08-23Implement bus_space_barrier() on sgi; on xbridge, this will also flushMiod Vallat
the pci write buffers.
2010-08-23Rework the logic of xbridge pci_conf_{read,write} to avoid doing the disableMiod Vallat
bridge interrupts dance when trying to access an uninplemented ioc3 register. Makes PIC handling simpler as a bonus.
2010-05-09Program a larger PCI retry hold interval if there is a Lucent USB controllerMiod Vallat
on the bus, to workaround timeout problems, according to IRIX knowledge which made its way to Linux.
2010-04-21more cleanup to cope with the change that tries to make proc.h not actTheo de Raadt
like it is everything.h ok tedu
2010-04-07Correctly initialize cursor attribute when this display is a console device;Miod Vallat
tested by marco@
2010-04-06Obtain struct sgi_device_location for the console input and output devices,Miod Vallat
and compare against them when attaching potential console drivers, to figure out whether they indeed are acting are console devices or not.
2010-04-06Provide WIDGET_ID_FOO() macros to extract parts of the ID register value,Miod Vallat
instead of duplicating tedious mask and shift constructs MAXINT times.
2010-04-02Remove parent/slave mode of rbus as nothing uses it.Jonathan Gray
ok kettenis, sgi usage of rbus_new_body() pointed out by miod
2010-03-28Correctly account devio usage, instead of relying upon unused devio registersMiod Vallat
being set to zero; this allows a full PIC bus to correctly configure I/O resources. While there, when initializing a ppb, setup I/O resources before memory resources; without this a ppb connected to a PIC could not get I/O resources if devices behind it would use both I/O and memory resources.
2010-03-21let this compile without DIAGNOSTIC; from miodTheo de Raadt
2010-03-21Fix widget probe order for BASEIO boards and P-Brick.Miod Vallat
2010-03-13Make sure non-console impact_screen struct gets zeroed upon allocation,Miod Vallat
otherwise backing store may not get allocated for it; "go ahead" kettenis@
2010-03-08Correctly initialize all members of struct wsemuldisplaydev_attach_argsMiod Vallat
before attaching wsdisplay; it was turning out harmless but using more cpu time for nothing than necessary. ok deraadt@
2010-03-08fix a miod typo (it has to be a typo; miod makes no real mistakes)Theo de Raadt
2010-03-07Minimalistic driver for the ImpactSR (Mardigras) video option found on olderMiod Vallat
Octane systems, as well as some Onyxes. With special permission to change a systemwide .h file and add a manpage from deraadt@ Magic numbers and operation sequencing borrowed from Linux; tested on Octane + ESI. ok deraadt@
2010-03-07Allow iockbc(4) and odysseey(4) to act as console devices and attach early;Miod Vallat
this gives us working glass console on Fuel, as well as on Octane systems with Odyssey graphics. Joint work with jsing@
2010-03-07Add an MD interface for PCI drivers to be able to retrieve the node and widgetMiod Vallat
number the PCI bus they are on is connected to. Will be used shortly to help the console device selection logic.
2010-03-06Fix typos.Joel Sing
2010-03-04Introduce odyssey(4), a driver for the SGI VPro (aka Odyssey) graphicsJoel Sing
card, which can be found in Octane, Octane2, Fuel, Tezro and Onyx systems. ok miod@
2009-12-26Register an interrupt handler for PCI error conditions (as well as xtalkMiod Vallat
errors at the widget level). Extremely crude for now.
2009-12-25Pass both the virtual address and the physical address of the memory rangeMiod Vallat
when invoking the cache functions. The physical address is needed when operating on physically-indexed caches, such as the L2 cache on Loongson processors. Preprocessor abuse makes sure that the physical address computation gets compiled out when running on a kernel compiled for virtually-indexed caches only, such as the sgi kernel.
2009-11-26Now IPI can interrupt to clock interrupt handler.Takuya ASADA
It prevents deadlock with TLB shootdown and clock interrupt. ok miod@
2009-11-25IP30 IPI implementation.Takuya ASADA
Also few xheart modification for SMP. ok miod@
2009-11-25Allow xbow_intr_establish() callers to provide optional storage for theMiod Vallat
struct intrhand, instead of having it malloc()'ed.
2009-11-19It turns out that the 2GB contiguous DMA direct map window also needsMiod Vallat
to be aligned on a 2GB boundary. Therefore the `add 512MB' bit used on Octane does not give us a 0.5GB-2.5GB usable DMA range, but a 0.5GB-2GB range; trying to use address in the 2GB-2.5GB range would cause PCI DMA errors at the xbridge level. There is no real benefit in using it, since this required us to keep subtracting or adding 0.5GB when converting DMA address to physical memory address or the other way around. So stop using it; this makes a few parts of the code simpler (and until bounce buffers are implemented, Octane systems will not use more than 1.5GB of memory).
2009-11-18Move widget register information apart from xbow software interface, andMiod Vallat
update #include needs. No functional change.
2009-11-12Move the interrupt makemasks() code to the interrupt template; no functionalMiod Vallat
change.
2009-11-11It turns out PCI IOC3 card which embed both the Ethernet controller and theMiod Vallat
superio chip interrupt on two different pins (yet do not advertize themselves as a multi-function device, of course). So, on one hand, this makes the ioc attachment code simpler, because it simply needs to map interrupt pins A and B, and another hand, this moves all the interrupt knowledge to the PCI bridge driver, since routing of pin B differs whether the device is the onboard IOC3 chip (and able to use any of the 8 bridge interrupt sources...) or on a PCI board (with pin mapping sane, since controlled by the bridge). This makes superio interrupts on CADduo boards work. Tested to cause no regressions on Origin 200, Octane and Fuel.
2009-11-08Add code to send L1 commands and parse command results; use it to add a wayMiod Vallat
for IP35 systems with IOC3 onboard Ethernet to get their Ethernet address since it's no longer stored as an owmac(4) device on the IOC3 device itself.
2009-11-07Replace option TGT_ORIGIN200 and TGT_ORIGIN2000 with a single option,Miod Vallat
TGT_ORIGIN, which enables support for all IP27 and IP35 systems. The original two options have always been used together, and go back to when pefo thought supporting multiple nodes would be significant work. Since an Origin 200 can be a dual-node system, making a distinction between single node and multiple node systems is a moot point anyway. Be sure to rerun config(8) before rebuilding a kernel.
2009-11-07Change sgi system identification from a single system type list, to a smallerMiod Vallat
system type list (which really is the system family) and a subsystem type. No functional change yet.
2009-10-31Blinkenlichten on Octane.Miod Vallat
2009-10-26Rename struct confargs to struct mainbus_attach_args for consistency and alsoMiod Vallat
to prevent further abuse of it.
2009-10-26Make pci_intr_string() on xbridge return both the xbridge irq and the crossbowMiod Vallat
irq we route it to; this makes clear that devices connected to different xbridges but using the same xbridge irq are actually not shared at all; and this also helps figure out which device cause spurious interrupts.
2009-10-26Add support for the Octane power button to power(4). Took me a while toMiod Vallat
figure out how the interrupt was routed from xbridge to xheart... (it bypasses the regular `have xbridge send a xio interrupt packet' mechanism)
2009-10-26Add new xbow routines to explicitely trigger or clear an interrupt source,Miod Vallat
instead of embedding that knowledge in xbridge(4); will be used elsewhere shortly.
2009-10-22Completely overhaul interrupt handling on sgi. Cpu state now only stores aMiod Vallat
logical IPL level, and per-platform (IP27/IP30/IP32) code will from the necessary hardware mask registers. This allows the use of more than one interrupt mask register. Also, the generic (platform independent) interrupt code shrinks a lot, and the actual interrupt handler chains and masking information is now per-platform private data. Interrupt dispatching is generated from a template; more routines will be added to the template to reduce platform-specific changes and share as much code as possible. Tested on IP27, IP30, IP32 and IP35.
2009-10-22With the splx() changes, it is no longer necessary to remember which interruptMiod Vallat
sources were masked and saved in ci_ipending, as splx() will unmask what needs to be unmasked anyway. ci_ipending only now needs to store pending soft interrupts, so rename it to ci_softpending.
2009-10-22The recent cleanups make blatantly visible that the pending_int handlerMiod Vallat
does almost exactly what splx() is doing if ipending is zero, and triggers soft interrupts as well. So don't bother checking for ipending in splx, and always invoke pending_int, which gets renamed as splx_handler for consistency.
2009-10-22Replace intrmask_t with uint32_t. This types only describes interrupt masksMiod Vallat
in the coprocessor 0 status register (coupled with ICR on rm7k/rm9k), and may be completely alien to real hardware interrupt masks, so don't make things unnecessary confusing.
2009-10-22Introduce a logical xbpci(4) device between xbridge and pci, since more thanMiod Vallat
one pci bus can attach to an xbridge (if PIC) and both being `bus 0' would make dmesg confusing. While there, seize the opportunity of this new dmesg line to display the bus mode (PCI or PCIX) and speed.
2009-10-16Make Octane kernels compile again after recent changes. My bad.Miod Vallat
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