| Age | Commit message (Collapse) | Author |
|---|
|
fails after an escape character, and while there put explicit casts to
l1_command_build() variadic arguments.
|
|
|
|
for IP35 systems with IOC3 onboard Ethernet to get their Ethernet address
since it's no longer stored as an owmac(4) device on the IOC3 device itself.
|
|
attach, print it, and decide how many RX descriptors to use accordingly.
|
|
lack of such hardware.
|
|
|
|
as the onboard ioc device, if one has already been found on this node.
Also, on Origin 300, do not attempt to attach the PS/2 controller on the
onboard ioc(4) since PS/2 ports are not wired.
|
|
|
|
|
|
TGT_ORIGIN, which enables support for all IP27 and IP35 systems. The original
two options have always been used together, and go back to when pefo thought
supporting multiple nodes would be significant work. Since an Origin 200
can be a dual-node system, making a distinction between single node and
multiple node systems is a moot point anyway.
Be sure to rerun config(8) before rebuilding a kernel.
|
|
system type list (which really is the system family) and a subsystem type.
No functional change yet.
|
|
anymore, as this causes the nsphy connected to the onboard iec to sometimes
disappear after a warm boot.
Unfortunately this brings back the long reboot times on Origin 200, despite
still asking for no memory test.
|
|
ok miod@
|
|
would stop RX operation if it had to cross a 4KB boundary during receive).
|
|
|
|
header is properly aligned; speeds up RX buffer -> mbuf copies.
|
|
while there, silence overzealous messages when the TX empty interrupt fires
before we disable it.
|
|
- double the number of rx buffers.
- copy packets of 104 bytes or less entirely in the tx descriptor, instead of
only doing this for packets smaller than an Ethernet header.
- correctly disable the rx threshold interrupt. Otherwise, one received
frame every 64 would not be handled because we are not using this interrupt.
|
|
00:00:00:00:00:00, in order to trigger the code which will assign a `feel bad'
random address.
|
|
for the new iec(4) driver. Reminded by brad@
|
|
far, and needs help to figure out its Ethernet address on IP35 systems.
Heavily derived from mec(4) written by Izumi Tsutsui and Christopher Sekiya,
although it required many changes to fit the IOC3 chip.
|
|
spotted by deraadt@
|
|
|
|
|
|
|
|
|
|
to prevent further abuse of it.
|
|
a frame and clock interrupt doesn't need a struct intrhand.
|
|
irq we route it to; this makes clear that devices connected to different
xbridges but using the same xbridge irq are actually not shared at all; and
this also helps figure out which device cause spurious interrupts.
|
|
onboard ioc(4) devices, and on Octane this is always a DS1687 wired to
IOC3 bytebus #1 and #2, while on Origin this is always a DS1742 wired to
IOC3 bytebus #0.
|
|
figure out how the interrupt was routed from xbridge to xheart... (it bypasses
the regular `have xbridge send a xio interrupt packet' mechanism)
|
|
instead of embedding that knowledge in xbridge(4); will be used elsewhere
shortly.
|
|
interrupts and child device attachment).
|
|
specified in the kernel configuration file, but is provided by macebus(4)
as part of the child device attachment args, and provide both crime and
mace interrupt bitmasks; this allows us to only really enable interrupt
sources we care about, and to avoid invoking interrupt handler we don't need
to for the few mace interrupts multiplexed at the crime level.
|
|
sources on level 1.
|
|
logical IPL level, and per-platform (IP27/IP30/IP32) code will from the
necessary hardware mask registers.
This allows the use of more than one interrupt mask register. Also, the
generic (platform independent) interrupt code shrinks a lot, and the actual
interrupt handler chains and masking information is now per-platform private
data.
Interrupt dispatching is generated from a template; more routines will be
added to the template to reduce platform-specific changes and share as much
code as possible.
Tested on IP27, IP30, IP32 and IP35.
|
|
sources were masked and saved in ci_ipending, as splx() will unmask what needs
to be unmasked anyway. ci_ipending only now needs to store pending soft
interrupts, so rename it to ci_softpending.
|
|
|
|
Still unimplemented for now.
|
|
does almost exactly what splx() is doing if ipending is zero, and triggers
soft interrupts as well.
So don't bother checking for ipending in splx, and always invoke pending_int,
which gets renamed as splx_handler for consistency.
|
|
coprocessor 0 sr level might come back in the future if hardware support
requires it, but at the moment it's getting in the way of larger changes.
``In the Attic, noone can hear you scream''
|
|
in the coprocessor 0 status register (coupled with ICR on rm7k/rm9k), and
may be completely alien to real hardware interrupt masks, so don't make
things unnecessary confusing.
|
|
one pci bus can attach to an xbridge (if PIC) and both being `bus 0' would
make dmesg confusing.
While there, seize the opportunity of this new dmesg line to display the
bus mode (PCI or PCIX) and speed.
|
|
IP35 systems.
|
|
|
|
and no base has been enforced. Otherwise the leading number of the mec(4)
08:00:69:xx:yy:zz Ethernet address would be interpreted as octal base,
followed by an out-of-range `8' which is now rejected but incorrectly
skipped; noticed by maja@
|
|
bsd) unless some other object has changed. Rebuild and reinstall
in /usr/src/usr.sbin/config/ after updating!
"I like it" deraadt@
|
|
|
|
|
|
on all systems but O2 (to catch up soon). Also use the IOC4 MCR register to
figure out the IOC4 clock, instead of checking the widget control register,
to be consistent with iof(4).
|
