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2012-10-26Previous revision would prevent grtwo(4) boards from being recognized.Miod Vallat
Make sure that what seems to be a 8-bit ID register of value zero does not match as an expansion board, which it can't be, and continue with the specific frame buffer test logic.
2012-10-19Be sure to compile boot block objects with -D_NO_ABICALLS, to prevent .S filesMiod Vallat
in libkern from getting a ".abicalls" pseudo-op from including <machine/asm.h>; this will in turn flag the .o file as PIC even though it doesn't contain PIC code, really. This gets rid of the annoying "linking PIC files with non-PIC files" warnings spewed by ld at link time.
2012-10-19Link boot64 twice, first as a self-contained binary, to enforce there are noMiod Vallat
unresolved symbols, then as a relocatable image as initially intended. This will prevent the arcbios.c 1.18 breakage from occuring again.
2012-10-18Put back the kl_n_shift variable, removed by mistake in 1.18, causing theMiod Vallat
boot blocks to fail on IP27 and IP35 (IP26, IP30 and 32-bit ARCBios systems unaffected). While there, provide a simpler ARC_Call() macro for 32-bit boot blocks, and put a few more variables and statements within explicit __LP64__ guards. Crank boot blocks version as well.
2012-10-17Swap arguments to wdog_register() since it is nicer, and prepareTheo de Raadt
wdog_shutdown() for external usage.
2012-10-08Revamp the sequences for suspend/hibernate -> resume so that the codeTheo de Raadt
paths are reflexive. It is now possible to fail part-way through a suspend sequence, and recover along the resume code path. Split DVACT_SUSPEND by adding a new DVACT_POWERDOWN method is used after hibernate (and suspend too) to finish the job. Some drivers must be converted at the same time to use this instead of shutdown hooks (the others will follow at a later time) ok kettenis mlarkin
2012-10-03Don't include <mips64/archtype.h> unless you really need it.Miod Vallat
2012-10-03Split ever-growing mips <machine/cpu.h> into what 99% of the kernel needs,Miod Vallat
which will remain in <machine/cpu.h>, and a new mips_cpu.h containing only the goriest md details, which are only of interest to a handful set of files; this is similar in spirit to what alpha does, but here <machine/cpu.h> does not include the new file.
2012-09-29Work in progress support for the Power Indigo2 R8000 system (IP26). This isMiod Vallat
basically an IP22 system (R4000 Indigo2) with the ECC memory board of IP28, and a so-called ``streaming'' L2 cache. IP26 kernels currently boot single-user, but don't live long; I am suspecting a bug in the tcc cache routines, but am currently not able to find it (come to think of it, my understanding of how this cache works could be wrong, and of course there is no documentation for it but what can be gathered from IRIX' <sys/IP26.h> comments and defines). Hopefully this situation will improve in the near future; in the meantime I am commiting this as `work in progress' to make sure this code doesn't get lost.
2012-09-29Bring the `let decide ARCBios address at runtime' code to the SGI bootblocks,Miod Vallat
which allows them to run on IP26 (POWER Indigo2 R8000). Crank boot blocks version.
2012-09-29Store the base value of coprocessor 0 system register, when running userland,Miod Vallat
into a global. This allows R12000 O2 systems to set the DSD bit in once for all, instead of having to set it every time in setregs().
2012-09-29Handle the coprocessor 0 cause and status registers as a 64 bit value now,Miod Vallat
as some odd mips designs need moro than 32 bits in there. This causes a lot of mechanical changes everywhere getsr() is used.
2012-09-29Kill the mostly unused VMTLB_xxx and VMNUM_xxx defines. Move all tlbMiod Vallat
knowledge to <machine/pte.h>. Add specific routines for tlb handling setup (at cpu initialization time) and tlb ASID wrap.
2012-09-29Introduce assembly macros for specific processor hazards: tlb update, statusMiod Vallat
register update, status register update causing a change to the interrupt enable flag, and a few other arcane ones. <mips64/asm.h> will provide (supposedly sane) defaults, and <machine/asm.h> may override these with better tuned versions. Use these macros instead of random strings of nop in the various .S files requiring hazard workarounds.
2012-09-29Use a much simpler linker script for the kernel, adapted from loongsonMiod Vallat
2012-09-29Proide a mips_sync() macro to wrap asm("sync"), and replace gazillions ofMiod Vallat
such statements with it.
2012-09-27enable smscJonathan Gray
2012-08-31Move sgi/stand to plain -fno-pie -nopie. Binaries are the same.Pascal Stumpf
tested by and ok deraadt@
2012-08-29Implement pci_min_powerstate().Mark Kettenis
2012-08-28Add -nopie to LINKFLAGS on ELF architectures. Note that this needs anPascal Stumpf
updated gcc and ld to understand the new -nopie flag. ok deraadt@
2012-08-23kill nnpfs deadTheo de Raadt
2012-08-22Build the kernel with -fno-pie. Just getting Ms out of my tree; this will bePascal Stumpf
cleaned up later. ok deraadt@
2012-08-21Add NOPIE= bits for sys/arch/*/stand to ensure that bootblocks will always bePascal Stumpf
built with -fno-pie. This gets the hairiest part of PIE out of the way ... ok deraadt@
2012-08-10simplify pckbc_xt_translation()Alexandr Shadchin
* call only for set translation on (once in /sys/dev/pckbd.c) therefore we can delete unused code. * change behavior (more standard) - return zero on success ok miod@
2012-07-18Attach non-frame buffer GIO devices with ga_product being the id gathered byMiod Vallat
gio_id(), not the whole 32 bit first word. Some boards with a 8-bit only ID register use the other 24 bits, sadly.
2012-07-18Hopefully correctly recognize GIO boards with a 8-bit only ID register, whichMiod Vallat
are not frame buffers. Thanks to Martin Boehme for donating such boards!
2012-07-18regenMiod Vallat
2012-07-18A couple more device IDs, thanks to Martin Boehme for donating boards!Miod Vallat
2012-07-18According to Linux, and just verified the hard way, the 8254 timer does notMiod Vallat
interrupt on Indy; do not use it on such systems. Then, bring back a clock0 at mainbus attachment to IP22 kernels, and attach it late in the autoconf process if no other device has claimed the clock yet. This means R4000 and R4400 based Indy may experience the lost clock interrupt processor errata again, until a better way to skirt it is found.
2012-07-16Forgot these files during the recent clock churning.Miod Vallat
2012-07-14A known errata of R4000 and R4400 processors, is that reading the internalMiod Vallat
counter register close to a trigger of the counter interrupt, may cause the interrupt not to be generated. This makes it a bad idea to use the internal counter both for the scheduling clock and for delay(). Therefore, on IP22 systems (and IP28 because it makes my life easier), use one of the two 8254 timers connected to the onboard interrupt controller as the scheduling clock source. Adapted from NetBSD.
2012-06-28Correctly register contiguous memory regions which start within the ARCBiosMiod Vallat
reported memory but end beyond it, such as > 1GB DIMMs in bank 0. Also, currently restrict physical memory usage to 1.5GB - there seems to be a bogus 32 bit truncation happening in the IP30 specific codepath, which in turns ends up causing the low memory alias region (and thus, the exception vectors and the NMI handler) to be overwritten, which I can't find from code inspection (does anyone has 2GB of Octane memory to spare?) Both issues reported and fix/workaround tested by Florentijn van Kampen, thanks!
2012-06-26create new machine/_float.h which is namespace clean. create a newTheo de Raadt
MI float.h which pulls in and defines the values that are needed from there, and repair sys/limits.h so that it defines the values it needs as well (depending on POSIX version, XPG version, etc). guenther has a more exact selection of that coming for limits.h. this also fixes a few mistakes for the vax. reviewed by kettenis and guenther.
2012-06-24Code for the external L2 cache controller on Indy/Indigo2 R4600SC and IndyMiod Vallat
R5000SC processor modules; these sport an up to 512KB, physically indexed, write-through L2 cache which is not connected to the canonical external cache interface of these processors (hence requiring specific code to drive it). The cache is enabled early and disabled before returning to ARCBios (for very nasty things happen otherwise). Tested on R5000SC, will be tested on R4600SC soon.
2012-06-24Add cache operation functions pointers to struct cpu_info; the variousMiod Vallat
cache lines and sizes are already there, after all. The ConfigCache cache routine is responsible for filling these function pointers; cache routine invocation macros are updated to use the cpu_info fields, but may still be overriden in <machine/cpu.h> on platforms where only one set of cache routines is used.
2012-06-17Using the LLAddr register to store our curcpu() pointer on R10k SMP kernelsMiod Vallat
was a nice trick, but this register is only 32-bit wide and will be sign-extended, which requires all cpu_info structs to be allocated within 2GB physical - something which may not be possible on some configurations. This diff changes IP30.MP kernels to no longer use LLAddr to store curcpu, but use unused fields of the MPConf structure in low memory, indexed with the physical processor id, which can be obtained from the Heart PRID register.
2012-05-30Correctly compute the IOC3 device mask on MENET boards.Miod Vallat
2012-05-29Make it possible to disable the Sync-on-Green signal by setting theMike Belopuhov
ARCBios environment variable OSLoadOptions to "nosog". Now everyone can enjoy running O2 without an SGI monitor and don't turn vegetarian afterwards. All the essential bits come from NetBSD's crmfb driver except they've chosen to use a "SyncOnGreen" variable not saved by the ARCS. Pointers and corrections from and ok miod, jsing
2012-05-29When writing the new volume header to disk, write back the wholeMatthew Dempsky
sector rather than just the bytes for the volume header itself. Silences the "sloppy I/O" warnings triggered by sgi's distrib scripts. tested and ok deraadt
2012-05-28The link state code does not work correctly on Indigo (IP20) and E++ GIO boardsMiod Vallat
and will report the link being down too aggressively. Better to always report the link as up - these systems and boards are single media only so it won't harm much. Unbreaks dhcp in the installer on these interfaces; found the hard way by sebastia@
2012-05-27Add a `L2 cache line size' member to struct cpu_info. This allows R4k code toMiod Vallat
stop abusing another field, and will be used by more routines RSN. No functional change.
2012-05-27Proper support for the so-called `fast mode' of the Indigo2 ECC memoryMiod Vallat
controller. In this mode, access to physical memory are not allowed to bypass the cache, and this allows the memory subsystem to run faster. Of course, some device drivers will require uncached memory access (e.g. for proper HPC DMA descriptor operation). New ip22-specific functions to switch between `fast mode' and `slow mode' are introduced. hpc(4) now provides read and write routines to fetch a dma descriptor from uncached memory into a local copy, and update it from said modified copy. On systems without the ECC MC, these will do nothing and operation will continue to access the uncached memory directly. On systems with the ECC MC, they will perform a copy, and the writeback will be done in slow mode. bus_dmamem_map() requests for DMA memory with BUS_DMA_COHERENT set in flags, which would return uncached memory, will now always fail on systems with the ECC memory controller. Drivers which really need uncached memory, and are aware of this particular setup, will now pass BUS_DMA_COHERENT | BUS_DMA_BUS1, which will let the request succeed. sq(4) will use all of the above to work mostly unmodified on ECC MC systems in fast mode. Finally, fast mode is enabled after autoconf. Tested on IP22 and IP28.
2012-05-27Decide once for all whether IP22/IP28 systems are running with the ECC memoryMiod Vallat
controller or not, and store this in a global variable. This is better than checking for the IP number everytime, especially since, according to IRIX header files, not all IP26 use the ECC memory controller (not that it matters much for us since we do not run on them yet)
2012-05-26Be more strict when specifying hpc child device attachments: specificMiod Vallat
onboard devices need only attach to hpc0 instead of hpc?. While there, remove hpc1 and hpc2 attachment from IP28 configurations, as these can not exist on Indigo2 systems.
2012-05-25On IP28, silently acknowledge bus errors which can be attributed toMiod Vallat
speculative execution, while in kernel mode, attempting to access bogus physical address through CKSEG[01] or XKPHYS. Surprisingly enough, an IP28 system can boot multiuser without triggering any such error; they will only show up if there is a lot of I/O (and thus, context switching).
2012-05-25Support for the POWER Indigo2 R10000 systems (IP28). Currently running withMiod Vallat
ECC checking disabled, which allows the existing Indigo2 drivers to run unmodified.
2012-05-22Make the multicast filter routine conform to the Party's standards. AdaptedMiod Vallat
from a (non-compiling) diff from Brad.
2012-05-22When setting up the multicast filter, use the ac_multicnt field of the arpcomMiod Vallat
struct to know if there are multicast entries, instead of counting the number of entries in the list. No functional change. From brad.
2012-05-20Make sure the generic bus_dmamem_alloc() routine restricts its allocation toMiod Vallat
the dma_constraint range. This allows the xbridge(4) bus_dma_tag_t to use the generic routines instead of rolling its own, now that the ATE code has been removed.
2012-05-18Port NetBSD's pci@gio driver for fast Ethernet expansion boards for theMiod Vallat
IP22 family. This is just the bridge so far, as the underlying pci drivers will need some changes to work (dc(4) does not work correctly yet, and tl(4) needs to be bus_dma'ified).
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