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display. Otherwise, we would panic in wsdisplay_cnattach(). miod@ OK
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For most framebuffers it is faster.
Other changes include:
o 24 bit support in tcx(4) for the S24 framebuffer
o accelerated cgsix(4) text console
o new cgtwelve(4) driver for the GS framebuffer
o improved serial driver code
o better keyboard support
The following framebuffers have not been tested but should work: cgfour,
cgeight and cgfourteen
These changes will require XF4 changes, to use Xwsfb instead of Xsun*, to be
commited later today.
Most of the work by me during the LSM and the week after, with code borrowed
from jason@, NetBSD (new serial code), and feedback from mickey@. Work on
pnozz(4) done by millert@
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- try to handle tx ring reclaim in bestart()
- if we pass over the high water mark, enable TX interrupts
- disable them again when the low water mark is passed
Thanks to mickey@ for enduring 4 versions of this =)
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these check were already OK but have been modified for consistency.
Problem found by Silvio Cesare.
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has been sitting in my tree for awhile)
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There are many interrupt handlers that assume that they don't need to do
any spl protection in their code because the interrupt of some level can't
be interrupted by an interrupt of the same level. The problem is that some
interrupt handlers have hardware levels that are lower then their "software"
levels.
Fix this by adding an additional field to struct intrhand that specifies which
"software" level an interrupt handler has and blocks that level while handling
the interrupt. This new field is initialized in intr_establish which gets
an additional argument (which can be -1 meaning that the interrupt handler
doesn't need to block any additional level).
ok deraadt@
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usable in MD code in the future.
deraadt@ ok
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ra->ra_name is needed and is the result of getpropstring
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Instead of using a homegrown set of variables in this case, rely on uvmexp
fields once uvm has been initialized.
This requires a few #include <uvm/uvm_extern.h> here and there in the kernel
as well.
Idea from art@, changes by me.
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we're OACTIVE and cleared at least one slot
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we were IFF_OACTIVE and we freed at least one slot.
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headers.
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* check the qualify the intr pending bits with the enable bits
* enable/disable the cs4231 IEN bit in the pin control register
* move the cs4231 (not dma) interrupt handling to the general interrupt processing
[This properly allows for sharing with, eg. magma]
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64Mhz vs. the "normal" 25Mhz). This (with the cs4231 patch) makes this
board work.
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(This fixes the crash in pr2212, but the magma still doesn't want to
talk to the world... looks like oscillator problems).
[Many thanks to John Baker <jdbaker@blkbox.com> for donating a MAGMA board
for testing]
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the response queue. Instead of the ad hoc ISP_SWIZZLE_REQUEST, we now have
a complete set of inline functions in isp_inline.h. Each platform is
responsible for providing just one of a set of ISP_IOX_{GET,PUT}{8,16,32}
macros.
The reason this needs to be done is that we need to have a single set of
functions that will work correctly on multiple architectures for both little
and big endian machines. It also needs to work correctly in the case that
we have the request or response queues in memory that has to be treated
specially (e.g., have ddi_dma_sync called on it for Solaris after we update
it or before we read from it).
One thing that falls out of this is that we no longer build requests in the
request queue itself. Instead, we build the request locally (e.g., on the
stack) and then as part of the swizzling operation, copy it to the request
queue entry we've allocated. I thought long and hard about whether this was
too expensive a change to make as it in a lot of cases requires an extra
copy. On balance, the flexbility is worth it. With any luck, the entry that
we build locally stays in a processor writeback cache (after all, it's only
64 bytes) so that the cost of actually flushing it to the memory area that is
the shared queue with the PCI device is not all that expensive. We may examine
this again and try to get clever in the future to try and avoid copies.
Another change that falls out of this is that MEMORYBARRIER should be taken
a lot more seriously. The macro ISP_ADD_REQUEST does a MEMORYBARRIER on the
entry being added. But there had been many other places this had been missing.
It's now very important that it be done.
For OpenSD, it does a ddi_dmamap_sync as appropriate. This gets us out of
the explicit ddi_dmamap_sync on the whole response queue that we did for SBus
cards at each interrupt. Now, because SBus/sparc doesn't use bus_dma, some
shenanigans were done to support this. But Jason was nice enough to test the
SBus/sparcv9 changes for me, and they did the right thing as well.
Set things up so that platforms that cannot have an SBus don't get a lot of
the SBus code checks (dead coded out).
Additional changes:
Fix a longstanding buglet of sorts. When we get an entry via isp_getrqentry,
the iptr value that gets returned is the value we intend to eventually plug
into the ISP registers as the entry *one past* the last one we've written-
*not* the current entry we're updating. All along we've been calling sync
functions on the wrong index value. Argh. The 'fix' here is to rename all
'iptr' variables as 'nxti' to remember that this is the 'next' pointer-
not the current pointer.
Devote a single bit to mboxbsy- and set aside bits for output mbox registers
that we need to pick up- we can have at least one command which does not
have any defined output registers (MBOX_EXECUTE_FIRMWARE).
Explicitly decode GetAllNext SNS Response back *as* a GetAllNext response.
Otherwise, we won't unswizzle it correctly.
Nuke some additional __P macros.
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misc pmap usage fixes.
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vm_map_t -> struct vm_map *
vm_map_entry_t -> struct vm_map_entry *
simple_lock_data_t -> struct simplelock
(uvm not done yet, coming in the next commit)
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(Look ma, I might have broken the tree)
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int (*d_mmap) __P((dev_t, int, int));
to:
paddr_t (*d_mmap) __P((dev_t, off_t, int));
This allows us to mmap devices past 4GB offsets.
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