Age | Commit message (Collapse) | Author |
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cpu_initialize.
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Inspired by a change in NetBSD pointed out by miod@.
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the ipi handlers.
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ok kettenis@
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on i386 and amd64. Don't let IPIs in when saving fpu context by disabling
interrupts.
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Suggested by miod@
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floating-point deferred-trap queue. Remove redundant code inherited from
sparc that deals with this. Also remove the code dealing with saving and
restoring the FPU state from unaligned memory; we always allocate properly
aligned memory for storing the FPU state.
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redundant since there is no queue to flush.
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invoking savefpstate in ipi_save_fpstate. ok kettenis@
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(and actually get reasonable values for the MB0 and MB1 sensors on the E250).
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to place. This is a nightmare, and we must move away from these stupid
wrapper APIs. ok kettenis
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more likely psycho) still has a bug where the pci bus croaks on the
intermittent i2c accesses. the spdmem accesses are safe, though.
if you wish to help us find out when this bug gets fixed, please run
your machine WITHOUT this diff, though.
ok kettenis jsg
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0/0 like the E250. Handle both.
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ok djm@ kettenis@
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ok miod@
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would fail from time to time on UltraSPARC-I and UltraSPARC-II CPUs.
Inspired by code in FreeBSD.
ok miod@
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There's enough code in here now, to add myself to the list of copyright
holders.
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on the Sun Enterprise 250. This device (and SUNW,envctrl found on the
Enterprise 450) is a PCF8584 I2C controller with several generic I2C chips
attached to it.
ok deraadt@
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in the MULTIPROCESOR case.
ok kettenis@
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for now.
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bsd.mp boot on an E250.
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ok deraadt@
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mark interrupts as busy.
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CPUs.
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ok deraadt.
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many.
ok deraadt@
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