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A few functions and symbols were included in non-VMM builds. This
tucks more of them behind the "#ifdef NVMM > 0" check and cleans
up RAMDISK kernels.
ok mpi@, feedback from chris@
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Some packets were dropped by vio_encap() when using bounce buffers.
These mbufs are too fragmented for the pre allocated bounce buffer
pages. By returing EFBIG the network driver will call m_defrag()
and try again. This fixes the problem.
OK sf@ hshoexer@
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ok gkoehler
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Bring the pieces for vmm(4) to support guests with SEV memory
encryption on AMD CPUs. The corresponding vmd(8) changes will
follow.
Emulate cpuid 0x8000001f so the guest can discover SEV features.
Allow vmd(8) to enable SEV on VM creation. Inform vmd(8) about the
c-bit position and ASID assigned to each VCPU.
Note that vmd(8) has to be rebuilt with the new header files.
from hshoexer@; input dv@; OK mlarkin@
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'no objection' kettenis@
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bss initialized.
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If the physical pages are contiguous, _bus_dmamap_load_buffer()
tries to merge the segments. In case of mbuf chains, it can happen
that the physical bounce buffers are contiguous, but the virtual
addresses of mbuf m_data are not. Then during transmit _bus_dmamap_sync()
tries to copy segments where it cannot access the virtual source
address which is mapped in a different mbuf. So if bounce buffers
are used, physical and virtual buffer must be contigous, to merge
a segment.
While there, split check and decrement of variable i in a for loop
to make the code readable.
with and OK hshoexer@
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controller drivers.
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With bounce buffers, we must pass a larger size to free()
ok bluhm@ hshoexer@
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There was an off-by-one bug when comparing the used pages for bounce
buffers with the available pages. As a result _bus_dmamap_load_buffer()
returned ENOMEM although there was one buffer left.
Also the _dm_nused field was updated and never reset in case of an
error. Use a local variable to count the used pages and update
global map->_dm_nused only if _bus_dmamap_load_buffer() was successful.
This fixes hanging network transmits if bounce buffers are enforced
for vio(4).
OK sf@ hshoexer@
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To debug bounce buffers easily on non-SEV hardware, introduce a
define FORCE_BOUNCE_BUFFER that activates them. Default is off,
no functional change.
OK miod@
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NULL means the same
ok kettenis
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ok miod@
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When running as SEV guest, as indicated by variable cpu_sev_guestmode,
allocate additional pages for each segment on dma map creation.
These pages are mapped with the PMAP_NOCRYPT attribute, i.e. the
crypt bit is not set in the PTE. Thus, these pages are shared with
the hypervisor.
When the map is loaded with actual pages, the address in the
descriptor is replaced by the corresponding bounce buffer. Using
bus_dmamap_sync(), data is copied from the encrypted pages used by
guest drivers to the unencrypted bounce buffers shared with the
hypervisor, and vice versa.
If the kernel is not running in SEV guest mode, which means as
normal host or non-SEV guest, no bounce buffers are used.
from hshoexer@; based on ancient code of mickey@; OK kettenis@
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This driver is not working yet, it's a copy of qwx(4) which bit-by-bit will be
adjusted to work on the newer generation of chips. Even though this is only a
minor bump over the previous generation, the changes are large enough that
bringup, debugging and long-term maintenance would suffer trying to squash them
into a single driver. This can be reconsidered once we have reached a stable
state.
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so mpi(4) gets removed from the floppy.
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Corrects an off-by-one error that results in EPT pte's not being
removed properly.
ok mlarkin@
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ok kn@
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ok mlarkin@, deraadt@
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If an interrupt-generating device does not have an interrupt-parent
property, its interrupt parent is assumed to be its devicetree
parent.
Implement this aspect of the spec in the same way as Linux does by not
just looking at the immediate parent but keep on walking up the tree
until we hit a node with an "interrupt-controller" property or a node
that has an "interrupt-parent" property.
similar diff as committed for arm64 a couple of days ago
ok jca@
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If an interrupt-generating device does not have an interrupt-parent
property, its interrupt parent is assumed to be its devicetree
parent.
Implement this aspect of the spec in the same way as Linux does by not
just looking at the immediate parent but keep on walking up the tree
until we hit a node with an "interrupt-controller" property or a node
that has an "interrupt-parent" property.
same diff as committed for arm64 yesterday
ok patrick@
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If an interrupt-generating device does not have an interrupt-parent
property, its interrupt parent is assumed to be its devicetree
parent.
Implement this aspect of the spec in the same way as Linux does by not
just looking at the immediate parent but keep on walking up the tree
until we hit a node with an "interrupt-controller" property or a node
that has an "interrupt-parent" property.
ok patrick@
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various Intel SoCs. The driver takes care of calling the AML methods
needed to enter low power idle states during suspend-to-idle (S0i).
The driver also implements some debug code that prints the residency of
various power states in dmesg. Based on some earlier code by jcs@
ok jcs@
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like the others.
Nudged, test, and ok deraadt@
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ok kettenis@
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This lets me boot the Samsung Galaxy Book4 Edge in DT mode with ufshci(4),
based on a WIP DTB file.
ok kettenis@
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Until now the kernel did panic during early boot because we couldn't
respond to the battery requests sent to the 0xa1 "bus". This (dummy)
driver registers a 0xa1 region space very early, and responds with a
static zero value to satisfy the battery requests on 0xa1, which let us
boot successfully to multi-user.
In the future this machine should be operated in FDT mode, and an improved
AML parsing interface might make this workaround obsolete also for RAMDISK.
Help and OK kettenis@, deraadt@
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CPU features.
ok naddy@
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us from trying to put devices into the D3 power state which some hardware
doesn't appreciate.
ok ratchov@, deraadt@
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restores the FPU registers (running in userland). And add an
".arch_extension nofp" afterwards such that the remaining kernel code
can't touch the FPU.
Needed to build with clang18
ok jsg@
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According to the AMD64 Architecture Programmer's Manual volume 2
the intercept SVM_INTERCEPT_INVLPGA needs to be set in vmcb.intercept1
(vector 3, offest 00Ch) instead of intercept2 (vector 4, offset
010h). SVM_INTERCEPT_INVLPGA is bit 26, so before vcpu_reset_regs_svm()
was actually setting an intercept for CR10, which does not exist.
from hshoexer@; OK mlarkin@
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otherwise clang 18 errors when inline assembly uses floating point
registers with nofp in -march
ok kettenis@
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registers from userland and set HWCAP_CPUID. This will allow detection
of features to be introduced into the architecture in the future without
allocating new HWCAP_xxx or HWCAP2_xxx bits. We provide the same
sanitized view of the CPU ID registers as is currently available through
sysctl(2).
Note that this introduces an unconditional read of ID_AA64MMFR2_EL1. This
is known to cause problems on older versions of QEMU. If this turns out
to be a problem in cases where updating QEMU is not an option, we'll have
to implement a workaround.
Also note that since we don't emulate the CPU ID registers on older core,
this means that microarchitectural optimizations keyed of reads of MIDR_EL1
are not possible on OpenBSD. I don't think that is a real problem.
ok jca@
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vmm(4) only supports using nested paging on Intel or AMD and no
longer supports HLAT or shadow paging.
ok mlarkin@
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Actually determine the C-bit position if we are running as a guest
with SEV enabled. Configure pg_crypt, pg_frame and pg_lgframe
accordingly, using the physical address bit reduction provided by
cpuid.
from hshoexer@; OK mlarkin@
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values and the feature bits that we recognize.
ok naddy@, jca@
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Input from miod@ and gkoehler@, tests & ok gkoehler@
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Input from miod@ and gkoehler@, tests & ok gkoehler@
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the stack utilization ends up near the the deep end of the stack where,
retcleans are useful. tested for a while in snaps
ok bluhm
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