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Based on imt(4)
Rename HIDMT_INPUT_MODE_MT to HIDMT_INPUT_MODE_MT_TOUCHPAD
ok deraadt
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ok deraadt@, krw@, jca@
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ok deraadt@
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ok patrick@
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are added. Presence of such MSRs is indicated with a feature flag, which
we probe and print at startup for each AP CPU. EFI screen scrolling hasn't
gotten faster (yet) and 9600 baud serial console is still the same speed
as 1980. Final piece of the puzzle is machines have more cpus, providing
more opportunity for screen scrolling and serial fifo's to fill up. The
BSP cpu is watching the AP cpus probe and print, but increased latency
causes it to exceed a timeout and print "cpuXX: failed messages".
Crank that timeout.
discussed with kettenis, ok guenther
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done on amd64 already. Original diff from Frank Groeneveld
ok tb patrick
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discussed with deraadt@ bluhm@ and sthen@
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This fixes the problem that which prevents typing the passpharase for
softraid on boot. It happened at least with some external keyboards
on ThinkPad X2{6,8}0. diff from Frank Groeneveld
ok tb
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nowhere.
ok kettenis@
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ok deraadt@ mlarkin@
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Based on a submisison from Jan Klemkow.
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The src/lib/libc/thread/rthread.c 1.8 change adds #include
<sys/atomic.h> in userland code.
Current m88k atomic.h contents are inside of #if defined(_KERNEL)
guard, then, nothing is defined for userland program.
So we need adding some defines to compile it on m88k.
The original diff is suggested from Miod Vallat, modified by the
advice from mpi@ and kettenis@.
ok kettenis@
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(1) Future cpus which don't have the bug, (2) cpu's with microcode
containing a L1D flush operation, (3) stuffing the L1D cache with fresh
data and expiring old content. This stuffing loop is complicated and
interesting, no details on the mitigation have been released by Intel so
Mike and I studied other systems for inspiration. Replacement algorithm
for the L1D is described in the tlbleed paper. We use a 64K PA-linear
region filled with trapsleds (in case there is L1D->L1I data movement).
The TLBs covering the region are loaded first, because TLB loading
apparently flows through the D cache. Before performing vmlaunch or
vmresume, the cachelines covering the guest registers are also flushed.
with mlarkin, additional testing by pd, handy comments from the
kettenis and guenther peanuts
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pseudo-device, get rid of the option. Enabling kcov now requires the following
line to be added to the kernel config:
pseudo-device kcov 1
This is how pseudo devices are enabled in general. A side-effect of this change
is that dev/kcov.c will no longer be compiled by default.
Prodded by deraadt@; ok mpi@ visa@
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land FPU context was saved to proc0. This was an information leak
as proc0 is used to initialize the FPU at exec and signal handlers.
Never save the FPU to proc0, it has the initialization value. Also
check whether the FPU has valid user land state that has to be
forked.
This bug is a regression from the eager FPU commit. OK guenther@
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move printing of ecxfeatures bits to match amd64
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ok patrick@
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OK deraadt@ mpi@
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provide our own FDT if the BIOS doesn't supply one, or even override
the supplied one.
Idea from and ok kettenis@
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with the syzkaller kernel fuzzer. So far, 8 distinct panics have been found and
fixed. This effort will continue.
kcov is limited to architectures using Clang as their default compiler and is
not enabled by default.
With help from mpi@, thanks!
ok kettenis@ mpi@ visa@
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for now as amd64/i386 firmware still caters for legacy OSes that only
support a single PCI segment.
ok patrick@
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needed for inserting and removing breakpoints through ptrace(2).
The approach here only works for CPUs that have a PIPT instruction cache
as we use aliased mappings to invalidate the instruction cache. That doesn't
work on CPUs that have a virtually indexed instruction cache.
ok deraadt@, visa@
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supported CPUs.
ok deraadt@, patrick@, visa@
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Inspired by an earlier diff from drahn@
ok patrick@, jsg@
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table and setting the bits atomically another core can select the
same ASID as we did it currently would not be safe to run it without
the kernel lock. This replaces the atomic_setbits_int(9) call with
atomic_cas_uint(9) where we can check that the table entry has not
been changed since we evaluted it. Also modify pmap_free_asid() to
use the same concept.
ok kettenis@
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It treats all access to the memory mapped registers as "secure" even if
we're running in non-secure mode. As a result, during bringup of OpenBSD
on the RK3399, I got confused and tweaked the interrupt priorities in a way
that is wrong (but worked on the RK3399.
Fix those priorities to match what they should be according to the
documentation (and works on other hardware that includes a GICv3) and
add code that detects the broken RK3399 GIC and adjusts the priorities
accordingly. Also remove (broken) code that tries to mess around with
group 0 interrupts and fix setting bits in the GICD_CTLR register on the
broken RK3399 GIC.
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and those that are indexed by the assigned CPU (unit) number. Fix the
shuffling of the affinity fields are shuffled around to match the spec.
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pmap_free_asid() and therefore pmap_destroy() mpsafe which is important since
we might end up calling that function without holding the kernel lock
as a result of releasing a reference in pmap_page_protect(9).
ok visa@
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'Deep Dive: CPUID Enumeration and Architectural MSRs'
ok deraadt@
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cases in kernel and libc.
ok deraadt@
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ok jsg@
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- Don't dereference sc_prop if we're not handling an LPI. Fixes a crash
on qemu when emulating a GICv3 without ITS (and therefore no LPIs(.
- Use the true IPL when calculating the priority of an LPI. The old
code used a variable that still had the IPL_MPSAFE flag in it.
- Write to the right GITS_BASERn instead of ialways writing to GITS_BASER0.
- Flush the cache after initializing/modifying the in-memory tables. The
GICv3 on the SynQuacer isn't fully coherent and only supports the
"non-shareable" attribute for its in-memory tables. So we have to flush
the cache to the point of coherency to guarentee that the GIC sees our
changes to those tables. Throw in a full memory barrier for good measure.
Also add support for the SynQuacer pre-ITS.
ok jsg@, patrick@
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ok jsg@, patrick@
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Fixes machines with more than 8 cores.
ok jsg@, patrick@
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Historically, the softraid crypto support in the boot loaders has only
given one attempt to provide the correct passphrase. There were a
few reasons for this, including the fact that pkcs5_pbkdf2() allows an
empty passphrase and that returning EPERM allowed for another attempt.
With the event of KARL and the need for bsd.booted with hibernate resumption,
this becomes much more of an issue - if you get the passphrase wrong you
fail to resume. There are also other situations like using /etc/boot.conf
to switch serial console, but an incorrect passphrase results in the config
not being read. Also, bcrypt_pbkdf() does not permit empty passphrases.
This reworks the softraid crypto support in the boot loaders so that it
loops requesting a valid passphrase until one is provided, or an empty
passphrase is entered (at which point it will abort).
ok mortimer@ tb@
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type 0 configuration requests correctly which results in devices on bus 0
appearing multiple times. Fix this by adding a quirk and match the
appropriate compatible string.
ok jsg@, patrick@
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so that we can include firmware-dependant code in generic drivers to be
able to extract metadata information like MAC addresses and out-of-band
interrupts from the ACPI/FDT tables.
ok kettenis@
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ok patrick@
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up to 24.
ok patrick@
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Discussed with kettenis@
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From Miod Vallat, "Go ahead" kettenis
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