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AgeCommit message (Collapse)Author
2012-07-09Remove apic_intrcount counting in the interrupt handlers. Not that usefulTheo de Raadt
anymore as a debugging tool, and it is in a rather critical path. ok kettenis
2012-07-09Remove a useless macroTheo de Raadt
2012-07-09After a resume, re-initialize the MTRR registers on the AP processorsTheo de Raadt
as well. This fixes very slow performance due to lots of uncached memory on buggy machines, for instance on very large memory thinkpad W500 and such. ok mlarkin kettenis sthen
2012-07-09Do not re-initialize ci_randseed on the primary cpuTheo de Raadt
ok kettenis
2012-07-09unify com at cardbus attachmentsTheo de Raadt
2012-07-08The comment above amd64_mrinit_cpu() was way too specific and wrong.Theo de Raadt
2012-07-08Move the hibernate utility pages up to account for the MP tramp page.Mike Larkin
ok deraadt@
2012-07-08apm_kqfilter() is gonePhilip Guenthe
ok nicm@
2012-07-08Don't need to worry about the ATI driver here anymore.Mark Kettenis
2012-07-05Concatenating strings doesn't require __CONCAT() (and must not in standard C)Philip Guenthe
ok miod@
2012-07-02Does not need to pull in "the world" eitherTheo de Raadt
ok jsing
2012-07-01Increase default and maximum text, data and stack size limits; this is requiredMiod Vallat
to build X at -O2 nowadays, as well as an increasing number of ports. Based upon a diff from Brad, with a few values stripped down to fit within the sun4/4c virtual address space limitation. Discussed with deraadt@
2012-07-01Do not define XDC_DIAG if option SMALL_KERNEL; shaves about 14KB, and allowsMiod Vallat
sparc floppies to fit again.
2012-06-30Further research shows that fp@x,y device path components with x > 0 areMark Kettenis
used by Solaris for virtual ports (NPIV), and booting from thos is not supported by OBP. Simplify the code accordingly.
2012-06-28Correctly register contiguous memory regions which start within the ARCBiosMiod Vallat
reported memory but end beyond it, such as > 1GB DIMMs in bank 0. Also, currently restrict physical memory usage to 1.5GB - there seems to be a bogus 32 bit truncation happening in the IP30 specific codepath, which in turns ends up causing the low memory alias region (and thus, the exception vectors and the NMI handler) to be overwritten, which I can't find from code inspection (does anyone has 2GB of Octane memory to spare?) Both issues reported and fix/workaround tested by Florentijn van Kampen, thanks!
2012-06-27Change sparc64 to match the "fp" boot device path's parameter based onMatthew Dempsky
the prototype-scsi_link's SDEV_2NDBUS flag rather than against its scsibus field. First, the scsibus field hasn't even been initialized when device_register() is called so it's always 0 anyway; second, the path number is supposed to be locally scoped to a single device whereas the scsibus field is a global scsibus(4) device number. The existing code only happened to work because all of the dual-port fibre-channel adapters we currently support attach as two devices with one scsibus each rather than a single device with two scsibuses, so we would never see anything but "fp@0". Initial investigation and diff by jmatthew after my SCSI cleanups at c2k11 broke sparc64's ability to boot from isp(4); newer version from me based on discussion with krw and kettenis. tested and ok kettenis
2012-06-26ALPHA_PGSHIFT -> PGSHIFT.Theo de Raadt
2012-06-26do not assume that sys/param.h is pulling in the world; pull in what isTheo de Raadt
needed by hand.
2012-06-26param.h (like landisk and alpha before) was still trying to include tooTheo de Raadt
much of the kernel world when it did not need to
2012-06-26create new machine/_float.h which is namespace clean. create a newTheo de Raadt
MI float.h which pulls in and defines the values that are needed from there, and repair sys/limits.h so that it defines the values it needs as well (depending on POSIX version, XPG version, etc). guenther has a more exact selection of that coming for limits.h. this also fixes a few mistakes for the vax. reviewed by kettenis and guenther.
2012-06-26Stop the song and dance where alpha param.h tries to include the world.Theo de Raadt
"Why is this not commited yet?" says miod
2012-06-25Turns out this file not need machine/float.h at all, since it definesTheo de Raadt
all the goop it needs by itself ok millert
2012-06-24Code for the external L2 cache controller on Indy/Indigo2 R4600SC and IndyMiod Vallat
R5000SC processor modules; these sport an up to 512KB, physically indexed, write-through L2 cache which is not connected to the canonical external cache interface of these processors (hence requiring specific code to drive it). The cache is enabled early and disabled before returning to ARCBios (for very nasty things happen otherwise). Tested on R5000SC, will be tested on R4600SC soon.
2012-06-24Bring in line with current cache_r{5,10}k.c style, and optimize slightly theMiod Vallat
handling of a partial last line in IOSyncDCache. No functional change.
2012-06-24Since the RM7000 cache behaves as a physically-indexed cache due to the setMiod Vallat
size being not larger than 4KB, use Hit operations on the pa instead of Index operations on the va for each set in the SyncDCachePage routine, when running with such a cache.
2012-06-24Get the L2 line size from the configuration register instead of hardcoding theMiod Vallat
smallest possible size; and on kernels with 16KB pages, where no virtual aliasing happens, use Hit operations on the pa instead of index operations on the va for all sets in the SyncDCachePage routine. Tested by mikeb@ on IP32 and myself on IP27/28/30/35
2012-06-24Do not output unnecessary semicolons when expanding macros. No functional changeMiod Vallat
2012-06-24Add cache operation functions pointers to struct cpu_info; the variousMiod Vallat
cache lines and sizes are already there, after all. The ConfigCache cache routine is responsible for filling these function pointers; cache routine invocation macros are updated to use the cpu_info fields, but may still be overriden in <machine/cpu.h> on platforms where only one set of cache routines is used.
2012-06-23Replace R5000 and R10000 family assembly cache routines with C equivalents,Miod Vallat
which will be easier to maintain on the long run. Be sure to rm cache_r*.d in your kernel compile directories after updating.
2012-06-23Fix ITLBNOPFIX macro definition on RM7000-capable kernels, and use itMiod Vallat
in cp0_set_config() for consistency.
2012-06-21Only allow the memory and mmio regions to be mmap()'ed at their realMartin Pieuchot
addresses, remove the magic value to uniformize access to the mmio and doesn't map the unused pseudo-vga registers. While here simplify the console attachement logic and removed some unused global variables. Tested by matthieu@ and myself on various different G3 and G4 models. ok kettenis@
2012-06-21__tfork() needs to set the stack address of the new thread in the kernel,Philip Guenthe
so that it can't get a signal while still running on the parent thread's stack. Also, pass in sizeof(struct __tfork) to provide forward compat when more members are added. This is an ABI change, so switch syscall numbers and bump lib majors this time. ok deraadt@ matthew@
2012-06-20move to 5.2-betaTheo de Raadt
2012-06-20RIP mac68k. No one loves you anymore.Matthew Dempsky
2012-06-20Fix some hibernate issues on machines with > 3.5GB phys memMike Larkin
ok deraadt@
2012-06-17No longer restrict alloc_contiguous_pages() to memory in the low 4GB.Miod Vallat
2012-06-17Using the LLAddr register to store our curcpu() pointer on R10k SMP kernelsMiod Vallat
was a nice trick, but this register is only 32-bit wide and will be sign-extended, which requires all cpu_info structs to be allocated within 2GB physical - something which may not be possible on some configurations. This diff changes IP30.MP kernels to no longer use LLAddr to store curcpu, but use unused fields of the MPConf structure in low memory, indexed with the physical processor id, which can be obtained from the Heart PRID register.
2012-06-17Remove leftover loongson or sgi references.Miod Vallat
2012-06-16fix bad grammar in a commentMiod Vallat
2012-06-11serial -> serial port; ok phessler@Otto Moerbeek
2012-06-10Document the "machine comaddr" command.Mark Kettenis
2012-06-10Document the "machine comaddr" command. Remove the text that (incorrectly)Mark Kettenis
states that only com0 can be used as serial console.
2012-06-10Always allow serial console, even if the BIOS doesn't report the presence ofMark Kettenis
any serial ports. Otherwise the new code to use puc(4) ports as serial console isn't all that useful. ok sthen@, miod@
2012-06-05As specified in PA RISC 2.0 errata, the 16-byte alignment restriction doesJoel Sing
not apply if the coherent operation cache control completer is specified for the ldcw/ldcd instruction. As a result, remove the alignment requirement and add the necessary completer. ok kettenis@
2012-06-05Implement actual mutexes for hppa64.Joel Sing
ok kettenis@
2012-06-04Fix serial port output.Marcus Glocker
OK weingart@
2012-06-04Correct the backwards compatibility code for console device configuration.Joel Sing
Fix tested by naddy@ ok kettenis@
2012-06-03Avoid the unlikely but possible use of an uninitialised variable.Joel Sing
ok kettenis@
2012-06-03Add support for serial consoles at non-standard addresses. This implementsMark Kettenis
a new "machine comaddr" command that makes it possible to configure the io port used to access the serial port. This can be used to use serial ports on a puc(4) device as serial console.
2012-06-01Ansify function definitions, fix some style(9) and whitespace issues.Joel Sing
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