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2017-04-08Bring over the changes I made to the armv7 version of this driver such thatMark Kettenis
interrupts are correctly routed to the boot cpu if that isn't the one connected to CPU interface zero on the interrupt controller. ok patrick@
2017-04-08Make network ports work on Shasta.Visa Hankala
2017-04-08Remove some #if 0 code that dates back to r1.1Mike Larkin
Pointed out by Michael W. Bombardieri
2017-04-07Add prid for CN72xx/CN73xx.Visa Hankala
2017-04-07Make SoC version available in a simple form.Visa Hankala
2017-04-06Use the correct interrupt disestablish routine.Visa Hankala
2017-04-06Extend the fdt interrupt API a little.Visa Hankala
2017-04-04Cleanup the code further. Get rid of the remaining C++-style comments,Mark Kettenis
remove some debug printfs, get rid of STATIC and __inline defines and remove a bit more unused code. ok drahn@, visa@
2017-04-04Issue memory barrier before lock release, not after. This ensuresVisa Hankala
the release write becomes globally visible only after any writes of the critical section are globally visible. In practice, the reordering has not happened because the kernel runs in the total store order mode. Tested by and OK kettenis@
2017-04-03Compute address for ll/sc only once.Visa Hankala
2017-04-02Filter out RDTSCP, needed to handle solaris guests. We set the VMX controlMike Larkin
to enable RDTSCP to 0, so when solaris attempted to use the instruction (since it wasn't filtered out of CPUID information), the CPU issued an #UD exception.
2017-04-02On ARMv8, the translation table walk is fully coherent so there is noMark Kettenis
reason to explicitly flush the cache before invalidating the TLB. The barrier that is included in out TLB flushing code should be enough to guarantee that the TLB walking hardware sees the updated page table contents, so the explicit barriers can go as well. Sanitize the code immediately surrounding the removed bits while I'm there. Tested by jsg@, ok drahn@, visa@
2017-04-02printf format strings should be literals. Reminded by clang.Visa Hankala
2017-04-02Drop address conversion cruft.Visa Hankala
2017-04-02Bring back the wait instruction into the idle loop, but only on octeon.Visa Hankala
This lets an idle SoC run a bit cooler. Tested on CN5020, CN6120 and CN7130.
2017-03-28Add an instruction synchronisation barrier instruction after changingJonathan Gray
the vfp state via cpacr_el1. This matches the advice given in the "Synchronization requirements for system registers" section of the ARMv8 ARM. Without this an overdrive 1000 with A1120 (Cortex A57 r1p2) reliably triggers "panic: VFP exception in the kernel" when init(8) is run. ok drahn@ kettenis@
2017-03-28Properly handle VMX entry controls governing guest processor mode.Mike Larkin
Before seabios, this didn't matter much but now it does since various bootloaders/kernels need such treatment. ok deraadt
2017-03-28add RDTSCP flags to identcpu.cMike Larkin
ok guenther, deraadt
2017-03-28Previous W^X diff only changed the access permissions in the bootstrap pageMark Kettenis
tables. We need to set them in the final kernel page tables as well. ok visa@
2017-03-28Reset ci_curmap to kernel_pmap() in cpu_hatch(). Otherwise the lazy pmapMark Kettenis
switching code might think the old pmap is still active after a resume which could lead to a page fault in the kernel. ok stsp@, mlarkin@, deraadt@
2017-03-27typo in debug buildMike Larkin
2017-03-27add a newline to an error printfMike Larkin
2017-03-27hibernate_free() should not be called from MD code, acpi_sleep_state()Theo de Raadt
unwinds that. Upon hibernate fail, this was a collection of double-frees.. ok claudio mlarkin
2017-03-26KNFJeremie Courreges-Anglas
2017-03-26discard MSR reads from unknown MSRs instead of passing them through. ThatMike Larkin
behaviour was needed during early development but not anymore. Suppress the printf that accompanied these exits since linux guests go probing wildly into msr-land on each boot. ok deraadt
2017-03-26Add "AVX" to the comment above the previous commit. Spotted by reykMike Larkin
2017-03-26Suppress AVX from the extended CPUID flags. Our AVX treatment is currentlyMike Larkin
incomplete and enabling it leads ubuntu guests to try and use the feature, with incorrect results. We can re-enable this at a later date when AVX is properly handled.
2017-03-26Switch arm64 generic timer to use virtual timer instead of physicalDale Rahn
timer. virtual timer will always be present where physical timer may be disabled by hypervisor. Other OSes use virtual timer. ok patrick@
2017-03-25Split vmm_probe() into a vmm_enabled() function, to better follow theTheo de Raadt
probe/attach approach used by mainbus. ok mlarkin kettenis
2017-03-25Use explicit operand with SVM instructions as clang doesn't recognize theMark Kettenis
implicit form. ok mlarkin@
2017-03-24Implement a driver for Marvell's AHCI controller. This is in essencePatrick Wildt
a generic AHCI controller with the twist that the MBUS window needs to be configured in the controller registers. This enables use of SATA on devices like the SolidRun ClearFog or Omnia Turris. ok kettenis@
2017-03-24Implement a driver for Marvell's XHCI controller. This is in essencePatrick Wildt
a generic XHCI controller with the twist that the MBUS window needs to be configured in the controller registers. This enables use of USB on devices like the SolidRun ClearFog or Omnia Turris. ok kettenis@
2017-03-24Simplify ASID allocation code considerably by allocating an ASID up frontMark Kettenis
when a pmap is created and freeing it when the pmap is destroyed. This diff relies on the fill 16-bit ASID space being implemented in the processor. While this is documented as an optional feature in the ARMv8 architecture reference manual, all ARMv8 processors seen in the wild so far implement the full 16-bit space. This change incorporates changes by drahn@ to allocate an empty page table for the lower half of the address space for the kernel. ok drahn@, patrick@
2017-03-24Bump resolution of frequencies from kHz to Hz, since that is what thePatrick Wildt
clock frequency API expects. Fixes login prompt over serial console.
2017-03-24Mainline u-boot on the ClearFog seems to insert an empty memory regionPatrick Wildt
into the /memory node which we happily physload into UVM. This leads to a quickly panic(9)ing system when there is actual physical memory starting at zero due to how the physeg array is sorted when using the binary search strategy. To fix this, do not physload an empty memory region. ok jsg@ kettenis@
2017-03-24Handle guest interruptibility state - Reset the interruptibility stateMike Larkin
VMCS field on vmentry when we advanced %rip on the last exit (simulating a real processor's behaviour). Handles guest "sti ; hlt" instruction sequences, which is used in seabios as a primitive idle loop construct.
2017-03-24Exit to vmd on byte size PCI accesses.Mike Larkin
2017-03-24Allow returns from vmd after handling cpuid exits (handles the case whereMike Larkin
a cpuid instruction was emulated at the same time there was an interrupt pending)
2017-03-23Bump the emulated PCI MMIO range end to 0xFFFFFFFF. This slightlyMike Larkin
penalizes i386 guests who previously had memory allocated by vmd after 0xF0FFFFFF (the previous range end) but makes memory range calculation in vmd/mc146818 much much easier. This diff needs to be combined with the previous vmd diffs or you won't be able to create a vm with memory size larger than ~3855MB.
2017-03-22Implement kernel W^X for arm64. For this purpose align the different segmentsMark Kettenis
containing .text, .rodata and .data/.bss at 2MB boundaries and set the appropriate access permissions on the block translations. ok patrick@
2017-03-21As a first step towards SMP, use an array for the destination masks withMark Kettenis
an element for each CPU. Use this mask directly instead of converting it into a cpu number and back into a mask again when routing interrupts. This avoids the need to handle uniprocessor systems in a special way as they will return 0 as the mask (the relevant register is defined as RAZ) and ignore what's written into the destination registers (the relevant registers are defined as WI). Future code that hatches the secondary CPUs will have to call into the driver to establish the masks for those CPUs. ok patrick@
2017-03-21Avoid panic in arm_sync_icache() by only flushing the parts of the addressMark Kettenis
space for which we have a userland mapping. ok jca@
2017-03-21Revise the definition of "struct reg" to have a layout compatible with otherMark Kettenis
operating systems. Implement process_read_regs() and make process_read_fpregs() clear the struct fpreg to avoid leaking kernel stack contents. This makes core dumps actually usable. ok drahn@
2017-03-21Don't allow the guest to clear CR0_NE or CR4_VMXE. While we should beMike Larkin
using the "must be clear / must be set" masks for these registers, I'd like to know (for now) when guest VMs manipulate bits in these registers in an unexpected way. This is needed for Linux guests, as they unconditionally set CR0 without NE, and CR4 without VMXE.
2017-03-21CPUID feature 0x80000000 emulation fell through to 0x80000001, whichMike Larkin
resulted in wrong cpu information being passed to the guest. Specifically this breaks Linux guests as with the fallthrough, CPUID_LONG was cleared, and Linux thought it was runinng on a machine incapable of 64-bit mode. OpenBSD/NetBSD guests don't check this flag and thus weren't affected.
2017-03-20Do not map resources which are actually not used within the kernel. SavesMiod Vallat
24KB of page tables memory. help and luna88k-2 tests aoyama@; ok aoyama@
2017-03-20Fix previous. Commited from the wrong tree.Miod Vallat
2017-03-20Remove unused defines. Some of them can be traced to MVME188 and make noMiod Vallat
sense on Omron hardware. ok aoyama@
2017-03-20Replace hardcoded addresses with symbolic constants from <machine/board.h>Miod Vallat
for enhanced grepability and fewer bad surprises. ok aoyama@
2017-03-19Put the address of the per-cpu clock and interrupt registers into the cpu_infoMiod Vallat
struct, rather than fetching them from arrays every time they are needed. ok aoyama@
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