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ok kettenis@ jmatthew@
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cannot handle the larger firmwares, so we must place them somewhere
else where the kernel can read them. Let's use 1MB. And pay attention
if someone gets burned by this decision. Other solutions get a lot
more hairy
ok mlarkin jsing
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operations. This resolves one of the failures frequently seen
on QEMU where spawning processes while another process is working
can lead to crashes.
Committing on behalf of drahn@
ok kettenis@ jsg@
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applications will crash without this lock as other threads attempt
to walk the tree while another thread is adding/removing mappings.
Committing on behalf of drahn@
ok kettenis@
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* define V_IGN_TPR (ignore virtual TPR)
* set V_IGN_TPR while configuring window exiting (was missed in one
location along with setting of the intr vector)
This should fix unresponsive network / console issues with guests on SVM.
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the brk area anyway.
- Use a larger hint bound to spread the allocations more for the 32-bit case
- Simplified the overy abstracted brs/stack allocator and switch of
guard pages for the brk case. This allows i386 some extra space,
depending on memory usage patterns.
- Reduce brk area on i386 to give the rnd space more room
ok stefan@ sthen@
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Don't use the standard pmap PTE functions to manipulate EPT PTEs. This
occasionally caused VMs to fail after random amounts of time due to
loading the pmap on the CPU and the processor updating A/D bits (which
are reserved bits in EPT). This ultimately manifested itself as errors
from vmd ("vcpu X run ioctl failed".)
tested by many, on different types of HW, no regressions noted
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The implementation tries to allocate sufficient memory to match the size of
the microcode file and will blow the boot loader heap when loading a larger
microcode file. This has been causing "heap full" errors at boot on some
machines.
Diagnosed with deraadt@
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ok deraadt, kettenis
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syscall) confirm the stack register points at MAP_STACK memory, otherwise
SIGSEGV is delivered. sigaltstack() and pthread_attr_setstack() are modified
to create a MAP_STACK sub-region which satisfies alignment requirements.
Observe that MAP_STACK can only be set/cleared by mmap(), which zeroes the
contents of the region -- there is no mprotect() equivalent operation, so
there is no MAP_STACK-adding gadget.
This opportunistic software-emulation of a stack protection bit makes
stack-pivot operations during ROPchain fragile (kind of like removing a
tool from the toolbox).
original discussion with tedu, uvm work by stefan, testing by mortimer
ok kettenis
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- provide struct cpu_info_full
- prepare K-U sections
- reorganize interrupt, trap, syscall entry to use K-U trampoline
- prepare pmap for entering special mappings, the mappings are not
setup yet
This code will already trigger performance issues. We do more tlb
flushes, but we do not unmap the kernel yet. The latter
will be needed to prevent Meltdown.
from hshoexer@; input guenther@; OK mlarkin@ deraadt@
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PROC_STACK() in the upcoming stack pointer checking diff and probably fixes
bugs where ptrace(2) and core dumps would report the wrong register state.
ok deraadt@
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of address celss in the child unit specifier should be fetched from the
interrupt controller node. Fix this as the current code doesn't work on
the MACCHIATObin for example.
ok patrick@
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a hardware-accelerated implementation of several encryption
and authentication algorithms for ipsec(4):
AES-CBC
AES-CTR
AES-GCM
AES-GMAC
HMAC-MD5
HMAC-SHA1
HMAC-SHA2-256
HMAC-SHA2-384
HMAC-SHA2-512
Please note that the driver is currently disabled.
OK deraadt@
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gmac.c is left untouched for now to preserve layering.
OK mikeb@, deraadt@
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It would be better if this was filled in at trap time.
ok guenther
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ok deraadt, guenther
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random data into the buffer that we feed the kernel.
ok deraadt@
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enforce W^X for runtime services. Do respect the bits that indicate that
mappings can be non-readable, non-executable or read-only though.
ok patrick@
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by making use of the iomuxc regmap. While there I realized that the
naming definitions for the first two bits of the register are wrong.
Thus, update the mask to include all lower bits and rename bit 1 to
denote "MPLL enable". This should be flipped last to turn it on.
ok kettenis@
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ref clock in imxccm(4). We can now also remove the global variable
that stored the pointer to the imxccm(4) softc.
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and sata ref clock in imxccm(4).
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clock in imxccm(4).
ok kettenis@
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SPI is already included and adding 32 means we skip the first 32 available
MSI vectors, which is quite disastous if we only have 32 vectors like on
the Marvell Armada 8040.
ok patrick@
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using the "a4x" bus tag for the non-console code in the fdt glue.
ok patrick@
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using the device tree.
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enable the PLL even if the (optional) "fsl,anatop" property is not
available or if the regmap cannot be found.
Suggested by kettenis@
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calling imxccm using a special function.
ok kettenis@
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the USB charging detect so that we can replace the current code in
imxccm(4).
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from the clock framework, and instead always pass the driver's softc
as function parameter.
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that when we tackle it again.
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has currently not been set correctly. The phy speed is based on
IPG clock, not the Ethernet PLL divisor. Also when we bumped the
frequency base from kHz to Hz, we missed to update the divisor as
well. Clarify the formula being used to calculate the phy speed
and make use of the clock framework.
ok kettenis@
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to make it compile when enabled.
from hshoexer@
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support for using U-Boot's network layer. Since arm64 and armv7's
efiboot(8) have the same heritance the diffs from arm64 simply applied
to armv7.
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