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AgeCommit message (Collapse)Author
2007-10-19Don't use "counter-timer" as clock interrupt source on MULTIPROCESSOR kernelsMark Kettenis
for now.
2007-10-19Use HDL2CELL when passing an OpenFirmware handle in prom_start_cpu. MakesMark Kettenis
bsd.mp boot on an E250.
2007-10-19remove old-school "cpu%d running" messages from default code pathsTheo de Raadt
2007-10-18Don't try to send IPIs to CPUs that aren't running (yet).Mark Kettenis
2007-10-18Add support for the Moosehead PS/2 controller as found on SGI O2 workstations.Joel Sing
ok miod@ deraadt@
2007-10-18Make sure interrupts are really enabled at the beginning of proc_trampoline,Miod Vallat
tested by deraadt@ jsing@
2007-10-18enter for obj@ building, otherwise dribbles happenTheo de Raadt
2007-10-18Define a new attribute, pckbcslot, which pckbc and gsckbc provide, and toMiod Vallat
which pckbd and pms attach. This makes it simpler to add new controllers pckbd/pms can attach to.
2007-10-18No need to include <machine/pte.h> here.Miod Vallat
2007-10-18Get rid of the silly union for mips pte. No functional change exceptMiod Vallat
pmap.h now includes pte.h.
2007-10-17Add the Intel ICH9 chipset.Brad Smith
Tested by damien@ ok dlg@
2007-10-17Use ldx (instead of ld) to load a pointer.Mark Kettenis
ok deraadt@
2007-10-17Let other people build sparc64 bsd.mp too.Mark Kettenis
2007-10-17MULTIPROCESSOR kernels need clock interrupts on secondary CPUs too, so don'tMark Kettenis
mark interrupts as busy.
2007-10-17Spin up secondary CPUs on MULTIPROCESSOR kernels. Works on UltraSPARC-IIIMark Kettenis
CPUs.
2007-10-17Do not clean up vers.c as it is not autogenerated anymore.Hans-Joerg Hoexer
ok deraadt.
2007-10-17Get proc_trampoline() ready for MULTIPROCESSOR.Mark Kettenis
2007-10-17Sanitize debug printf.Mark Kettenis
2007-10-17Proper TLB flushing for MULTIPROCESSOR kernels.Mark Kettenis
2007-10-17more unification between amd64 and i386 (API changes, but we thinkTheo de Raadt
noone else uses this acpi except the command); from Mike Belopuhov
2007-10-17replacement for the pctr codebase that can handle amd64 processors asTheo de Raadt
well (in fact, all 4 combinations of codebase and processor) written by Mike Belopuhov and Aleksey Lomovtsev
2007-10-16For MULTIPROCESSOR kernels, make cpu_switchto() set p->p_cpu.Mark Kettenis
2007-10-16Make lazy fpu context switching work for MULTIPROCESSOR kernels. Tested byMark Kettenis
many. ok deraadt@
2007-10-16Make lazy fpu context switching work for MULTIPROCESSOR kernels. Tested byMark Kettenis
many. ok deraadt@
2007-10-16Another cpu_switchto() leftover.Mark Kettenis
2007-10-16unsigned int is nicer than just unsignedTheo de Raadt
2007-10-16Do not expose the end of the proc_trampoline bowels to C code anymore, andMiod Vallat
get rid of the ``switchframe'' struct definition. As a bonus, this makes cpu_fork() simpler and unwastes 8 bytes of u area.
2007-10-16Fix the mtx_wantipl != IPL_NONE comparison in the ``have to spin''Miod Vallat
MULTIPROCESSOR case in mtx_enter.
2007-10-15Skip non-SPD EEPROMs.Mark Kettenis
somewhat confused ok deraadt@
2007-10-15catch privileged actions as well; hint from miod@Federico G. Schwindt
2007-10-14registred -> registeredMiod Vallat
2007-10-14Don't bail out after finding the first cpu.Mark Kettenis
2007-10-14enable wbngTheo de Raadt
2007-10-14Provide a way to attach spdmem(4) by faking an I2C bus with EEPROMs withMark Kettenis
contents from OpenFirmware. ok deraadt@
2007-10-14Implement OF_getproplen().Mark Kettenis
ok deraadt@
2007-10-14'expresion' -> 'expression'. Reported by Jung on tech@.Kenneth R Westerback
2007-10-14One more cpu_switchto() leftover.Miod Vallat
2007-10-14Disable timer/compare interrupts on the macebus. This prevents interruptJoel Sing
storms from occurring on IRQ 6. ok miod@
2007-10-13Enable interrupts in secondary processors before invoking cpu_switchto(),Miod Vallat
rather the expecting it to do this for us.
2007-10-13It is no longer necessary to fiddle with spl in cpu_idle_{enter,leave} nowMiod Vallat
that proc_trampoline has been fixed.
2007-10-13Be sure to spl0() in proc_trampoline, so that kernel threads start at IPL_NONE.Miod Vallat
2007-10-13There is no need to fiddle with spl in cpu_idle_{enter,leave}, actually.Miod Vallat
2007-10-13Remove leftovers art forgot to prune...Miod Vallat
2007-10-13Fix cpu_exit() comments to be more closer to reality.Miod Vallat
2007-10-13Do not splhigh() before invoking sched_exit(), sched_exit() will do it better.Miod Vallat
2007-10-13Various typos in comments; Joel SingMiod Vallat
2007-10-11enable puc(4) for GENERIC on armishStuart Henderson
ok deraadt@
2007-10-10prepare for the futureTheo de Raadt
2007-10-10GENERIC.MP dirs will show up here some timeTheo de Raadt
2007-10-10Disable PSL_POW code for now in cpu_idle_cycle, because it does not yetTheo de Raadt
do the cache flush / instruction cache disable / tlb invalidate dance. For some reason in a switchto world this suddenly matters or machines become really slow running NFS... huh? figured out with kettenis
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