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made testers of art's affinity diff go insane)
ok krw@ miod@
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- Split up run queues so that every cpu has one.
- Make setrunqueue choose the cpu where we want to make this process
runnable (this should be refined and less brutal in the future).
- When choosing the cpu where we want to run, make some kind of educated
guess where it will be best to run (very naive right now).
Other:
- Set operations for sets of cpus.
- load average calculations per cpu.
- sched_is_idle() -> curcpu_is_idle()
tested, debugged and prodded by many@
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faults on machines where we map nvram write-only (through the clock chip).
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As a small bonus this now actually zeroes the whole struct, not just the
non-varying sized part.
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doesn't need the second pmap =. "ok if you tested it" kettenis@
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with different locking mechanism. 88110 soft ipi are replaced with an
ipi callback which is checked upon return from exception (it can not be kept
as a softintr, as the generic softinterrupt code doesn't have per-cpu
pending softintr queues).
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CPU_INFO_FOREACH() only covers attached cpus. With drahn@, ok kettenis@
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remove the special casing in splassert().
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levels. This will allow for platforms where soft interrupt levels do not
map to real hardware interrupt levels to have soft ipl values overlapping
hard ipl values without breaking spl asserts.
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in the DEBUG code, since these values aren't used there anymore.
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ok miod@
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11h (Turion) still needs testing, so isn't part of this commit.
ok reyk@, marco@
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Firstly, don't keep identical data for each of the GARTs (we keep them
in sync, but there is one per cpu socket), all that varies is the
pci_tag_t, so just keep an array of those and have the rest of the
information once.
Secondly, don't keep the softc as a global, use the _cookie field of the
dmatag_t, that's what it's there for.
Finally, use dmamap_map to map the page tables, instead of the direct NC
map. This is because later changes to support PAT will be a lot easier
with one direct map (where we change the cacheability if needed), since
otherwise it's just asking for illegal cache aliases.
More changes will be upcoming.
Tested by a few people, with an without bigmem, thanks to those.
weingart@ liked the direction this is going, marco@ and kettenis@ oked it.
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a define needed to get to ``private'' functions that needs to be defined
5 or more times isn't much use and may cause namespace issues anyway.
Other archs will probably follow.
Discussed in portugal. "Hell yes" weingart@, ok kettenis@, no
objections miod@
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on amd64 as well.
ok dlg@
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ok jsg@
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acceleration it is a tad bit slow, so leave this disabled for now.
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ok miod@
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can be found in iBook G4 12".
Remove references for LCD panel sizes because the same device can be found
on different sized laptops and it has nothing to do with the trackpad.
Introduce a type variable that stores the device type: FOUNTAIN, GEYSER1 or
GEYSER2. This value helps deciding some of the device parameters and it gets
printed in the dmesg instead of the panel size.
Introduce "mouse button emulation" on multi-touch trackpads just like in
macos, so it's not needed to bind mouse buttons to the keyboard anymore:
Tap two fingers + mouse button = 3rd mouse button = right click
Tap three fingers + mouse button = 2nd mouse button = middle click
Discussed with and ok: miod@ and maja@
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try to be smart for the address range, uvm_pglistalloc() is smart enough
nowadays.
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so that they can invoke sched_init_cpu() before the scheduler starts,
which allows the horrible kluge in cpu_configure() to die.
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NetBSD.
ok kurt@, drahn@, miod@
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flushing the whole TLB block every time a pte is modified, store a bitmask
of pending flushes and do them at pmap_update() time. 88100 behaviour is
unchanged.
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exchange with zero; use it in the soft interrupt code to make it simpler
and faster.
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times hardclock() needs to be invoked; fixes clock drift found on 197DP
with SMP kernels.
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(and MVME327 SCSI and MVME376 Ethernet, to provide a complete system).
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used there).
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last month.
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change to work better.
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around the Number 0 Imagine-128 chip. Colormap support is still missing.
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ok deraadt@
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Rework nmi handling to handle ``complex'' NMI faster, and return as fast as
possible from the exception, without doing the AST and softintr dance.
This should avoid too much stack usage under load.
ok deraadt@
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