| Age | Commit message (Collapse) | Author |
|---|
|
#ifdef CRYPTO. noticed by marco@
|
|
ok marco@
|
|
ok marco@
|
|
|
|
ok toby
|
|
BIOSen it's a complete lie. Instead use the information from the memory
map like we do on i386.
ok weingart@, oga@
|
|
load bsd.rd but bsd.rd.IP## matching the IP code of the machine.
|
|
|
|
work, even after restoring TLB and exception code.
|
|
and then restart system (NMI on these systems aren't intended to be
recoverable).
|
|
and volume header partitions. This makes DIOCGPDINFO return correct results,
which in turn lets disklabel -A behave as intended.
|
|
curcpu when we were freeing a pmap. Tested and working for a few weeks
now, but I was a bit too busy to commit it earlier.
|
|
we have, in order to pick a widget enumeration order matching the PROM.
This is especially important when the boot path is in dksc() syntax.
|
|
used by onboard IOC chips, by forcing the IOC to trigger this interrupt,
and some help from the PCI bridge driver to report which interrupt has
fired through a fake PCI configuration register.
This works nicely on IP27 and IP35, but on IP30 the interrupt doesn't
happen, for some reason; so keep the existing heuristic in case the above
trick did not give us a valid interrupt number.
In case we got an interrupt, this will also detect IOC configurations where
there is actually one interrupt, should such configurations exist.
<rant style="beck">
I probably deserve to rot in hell for this abomination, but I won't mind
as long as the IOC designers who came with the bright ``let's use more than
one interrupt and defecate on the pci spec'' ideas are there, too.
</rant>
|
|
drivers with callback routines. While there, skip disabled or failed
components.
|
|
|
|
confusion. Make sure this function is invoked with interrupts enabled now.
|
|
a chip bug, which was supposed to be fixed in that particular revision of
the die but wasn't (tlbhandler.S 1.16).
Being lazy, I did not write a runtime selection of the appropriate TLB
handler code, although this was on my list.
It turns out that this fix confuses the hell of R10000 processors revision 3
(but not earlier 2.x revisions), to the point of making the Origin 200 here
hang so hard it would not even enter the NMI handler (don't ask me how I
figured this was the cause).
So it's time to choose the appropriate TLB handling flavour at runtime,
building the trampoline code from the fixed exception handler location
jumping to the handler address at runtime. As a bonus, kernels linked in
KSEG0 get the address computation optimized and thus a smaller trampoline
than before.
|
|
|
|
|
|
PCI buses on xbridge.
In addition to this, we now support the limited IOMMU, allowing memory
outside of the 2GB direct window to be used for DMA.
Only tested on XBridge chip so far; this lets an IP35 machine with
physical memory after the 2GB boundary run stable again.
|
|
which require it will provide their own _dmamem_alloc() in their own
bus_dma_tag_t.
While there, rename bus_dma_segment_t ds_vaddr member to _ds_vaddr to make
it clear this is an internal member.
|
|
|
|
|
|
|
|
|
|
there to trap.c which is its only user. This also cleans up multiple
inclusion of <machine/cpu.h> (because <machine/psl.h> includes it) in many
places.
|
|
|
|
component by component, from device_register().
IP27 and IP35 systems using the dksc() syntax get their dksc() syntax converted
to an ARCS bootpath, so the same logic will apply.
|
|
IP27 logic will obviously not work there.
|
|
servicing interrupts, correctly mask the other (marked as pending)
interrupts in imr. Otherwise we get another interrupt immediately for nothing
(which updates imr correctly the second time).
|
|
is bandaid until interrupt handling is made more sane.
|
|
interrupt masks.
|
|
any such interrupts marked as pending.
|
|
not all Sun mice run at the canonical 1200 bps, hop between 1200, 4800 and
9600 bps by paying attention to breaks on the line.
Attachement and engine code written 7 years ago for OpenBSD/sparc, except for
sparc64 com(4) attachment. Speed hop idea borrowed from Opensolaris.
This allows sparc and sparc64 users to run X11 without needing a configuration
file anymore, as it was in the XFree86 3.x days. Multihead configurations
will still need a minimal configuration file, though.
|
|
only once.
|
|
have one or the other option, we won't get said kernel entry
point. Ok oga@
|
|
unwanted matching logic.
ok oga@ deraadt@ miod@
|
|
significantly reduces the number of times the chip gets wacked at boot.
From brad, tested by me.
|
|
|
|
|
|
|
|
loader image (which we can safely overwrite) or the kernel image itself (in
case of netboot) and there is already code to move the kernel image out
of the free memory later on.
|
|
|
|
some simple glue to attach each port as a network interface.
|
|
OK deraadt@, kettenis@
|
|
|
|
|
|
|
|
MK48Txx). Entangled with preliminary changes which will hopefully eventually
lead to power(4) attaching on IP30 (but not finished yet).
|
