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in the MI code.
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process_write_regs().
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userland is allowed to change in psr.
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so don't use any in the 88110-specific parts of locore.
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a kernel 10-15% faster on the t1k. Don't do this for SMALL_KERNEL though,
otherwise the 4MB locked mapping for the data segment will be too small to
include a ramdisk.
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the motherboard eisa id, instead of using a ``one size fits all'' value which
is too large on more than half the eisa-capable alpha designs.
The id -> slot # logic is based on the alpha ECU configuration files, so we
should not perform worse than ECU itself (and see all slots ECU sees too).
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above the stack. Fix by mapping PIE into the first quarter of the address
space before stack. "will do for now" miod@
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several minutes by making pmap_resident_count() return 0 for the kernel pmap.
discussed with miod@
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we depended on the pageability of the kernel_map to map them which worked
most of the time, until we hit the most improbable case - when cpu_switchto
wanted to fault in the missing gdt page, which at this moment is Verboten.
kettenis@ ok
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provided by the PROM gets flushed out of the TLB before we install our own
trap table. Makes RAMDISK kernels work on T2 systems.
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problem and lots of register dumps to help the skilled user to fix the hardware.
Not compiled if option SMALL_KERNEL.
From NetBSD.
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sense on m68k. Give USRSTACK its real (HP-UX compatible) value instead of
computing it from HIGHPAGES.
No functional change.
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dino_intr_map(); rather than adding the missing cast, make the intent of
the code clearer by explicitenly testing for PCI_INTERRUPT_LINE being ff.
While there, enable the out-of-extent-range checks in dino_memmap() and
dino_memalloc() even if no option DEBUG, but return failure instead of
panicing.
discussed with and ok kettenis@ marco@
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after it was published. In particular, they changed the maximum cache
aliasing boundary from 1MB to 16MB.
It turns that on the PA-8700 the aliasing boundary is actually 4MB
(reported as such by the firmware at least). There are some comments
in the Linux code that suggest that HP never actually built PA-RISC
CPUs with an 8MB or 16MB aliasing boundary.
So raise the aliasing boundary to 4MB. This fixes the weird ps(1) problem
where it didn't print its own arguments correctly.
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them going negative - this consists of identifying a number of cases of
IO not going through the buffer cache and marking those buffers with
B_RAW - as well as fixing nfs_bio to show pending writes and reads through
the buffer cache via NFS
still has a problem with mishandling the counters I believe in the
async/sync fallback case where counters stay positive which will be
addressed seperately.
ok tedu@ deraadt@
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bother trying to probe more.
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configures when it can. ok kettenis@
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per-platform implementation, instead of selected members of it; this allows
us to get rid of some globals, and paves the way for better bridge support
on some models.
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uvm_map.c from requiring <machine/exec.h>.
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fp; from NetBSD
ok millert@
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- math.h shouldn't define FLT_EVAL_METHOD, but float.h should (per
C99). remove from math.h, and add proper definitions in float.h
ok millert@
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SUN4V to let it suspend strands (why does everyone invent own words for
hyperthreads?). This gives a huge performance boost when most of the
cpus are idle.
kettenis@ ok
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per-processor soft interrupt register is used for hardware clock-tick
counter interrupts. So make smp_signotify() use IPL_SOFTINT instead
such that we don't unintentionally trigger a spurious clock interrupt.
This seems to fix the timekeeping anomalies on the t1k.
tested by art@
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ok marco@ no objection miod@ need this for regress djm@ no objection krw@
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ok jsing@
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ok jsing@
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plugged to the bottom 4 PCI slots of AlphaServer 1000A (attaching to pci1
behind a ppb) to get interrupts.
No regressions on AlphaServer 800 (which do not have these extra slots).
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is not used yet, but this seems to ``warm up'' the eisa chips so that
accesses to the eisa bus later do not cause machine checks.
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instead of only the starting address. From NetBSD.
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Right now when mi_switch picks up the same proc, we didn't clear the
flag which would mean that every time we service an AST we would attempt
a context switch. For some architectures, amd64 being probably the
most extreme, that meant attempting to context switch for every
trap and interrupt.
Now we clear_resched explicitly after every context switch, even if it
didn't do anything. Which also allows us to remove some more code
in cpu_switchto (not done yet).
miod@ ok
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the PCI host bridge if we're not running on an UltraBook. Fix allocation of
bus number such that it works on machines that have OpenBoot 4.x.
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splbio and won't delay clock interrupts.
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of making it dynamic and the smallest value above the former three. Idea
from NetBSD.
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parameter and returns an aligned random load address for position
independent executables to use. This also adds three new vmparam.h
defines to specify the maximum address, minimum address and minimum
allowed alignment for uvm_map_pie() to use. The PIE address range
for i386 was carefully selected to work well within the i386 W^X
framework.
With much help and feedback from weingart@.
okay weingart@, miod@, kettenis@, drahn@
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For now, only one such flag is defined, PCKBC_CANT_TRANSLATE. It hints
pckbc that the device does not behave correctly to the ``set translation''
commands.
Set this flag if we are running on a Tadpole Ultrabook machine, which needs it.
This makes the built-in keyboard work correctly on this laptop (with the
help of the software translation pckbd diff).
tested & ok kettenis@
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gsckbd; the former will cause a proper translation page to be selected by
the keyboard.
Because of this, we no longer depend on the page the keyboard is left in
by the PDC (page 2 for all machines but the PrecisionBook, which is in
page 3), and there is no longer any need to use separate keyboard maps.
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restrict the memory allocation range in _dmamem_alloc().
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