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figure out how the interrupt was routed from xbridge to xheart... (it bypasses
the regular `have xbridge send a xio interrupt packet' mechanism)
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instead of embedding that knowledge in xbridge(4); will be used elsewhere
shortly.
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interrupts and child device attachment).
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specified in the kernel configuration file, but is provided by macebus(4)
as part of the child device attachment args, and provide both crime and
mace interrupt bitmasks; this allows us to only really enable interrupt
sources we care about, and to avoid invoking interrupt handler we don't need
to for the few mace interrupts multiplexed at the crime level.
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ok brad@ marex@
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sources on level 1.
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logical IPL level, and per-platform (IP27/IP30/IP32) code will from the
necessary hardware mask registers.
This allows the use of more than one interrupt mask register. Also, the
generic (platform independent) interrupt code shrinks a lot, and the actual
interrupt handler chains and masking information is now per-platform private
data.
Interrupt dispatching is generated from a template; more routines will be
added to the template to reduce platform-specific changes and share as much
code as possible.
Tested on IP27, IP30, IP32 and IP35.
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sources were masked and saved in ci_ipending, as splx() will unmask what needs
to be unmasked anyway. ci_ipending only now needs to store pending soft
interrupts, so rename it to ci_softpending.
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Still unimplemented for now.
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does almost exactly what splx() is doing if ipending is zero, and triggers
soft interrupts as well.
So don't bother checking for ipending in splx, and always invoke pending_int,
which gets renamed as splx_handler for consistency.
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coprocessor 0 sr level might come back in the future if hardware support
requires it, but at the moment it's getting in the way of larger changes.
``In the Attic, noone can hear you scream''
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in the coprocessor 0 status register (coupled with ICR on rm7k/rm9k), and
may be completely alien to real hardware interrupt masks, so don't make
things unnecessary confusing.
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one pci bus can attach to an xbridge (if PIC) and both being `bus 0' would
make dmesg confusing.
While there, seize the opportunity of this new dmesg line to display the
bus mode (PCI or PCIX) and speed.
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RM7000_ICR, instead of IMASK_EXTERNAL, since they are actually different
concepts. This code remains disabled since RM7000_ICR is not defined anywhere
at the moment.
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IP35 systems.
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Paves the way for instrusive upcoming changes.
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us via splx().
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`restore cpl and invoke hw_setintrmask' slippery dance, just invoke splx().
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forgotten long ago and lingering in one of my trees since then...
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and no base has been enforced. Otherwise the leading number of the mec(4)
08:00:69:xx:yy:zz Ethernet address would be interpreted as octal base,
followed by an out-of-range `8' which is now rejected but incorrectly
skipped; noticed by maja@
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bsd) unless some other object has changed. Rebuild and reinstall
in /usr/src/usr.sbin/config/ after updating!
"I like it" deraadt@
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on all systems but O2 (to catch up soon). Also use the IOC4 MCR register to
figure out the IOC4 clock, instead of checking the widget control register,
to be consistent with iof(4).
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and add comments explaining why it's very unlikely we'll ever see TIO
widgets on mips-based SGI systems (unless someone builds a Mengele-style
XIO link).
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widget; make sure we reserve its address span so that no device risks
having its resources overlap the PROM.
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invalidation is necessary. Help jsing@
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running on, and report this both as the hw.product sysctl and in dmesg.
Fuel and Origin 350 are no longer reported as being Origin 300 systems!
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the *{X,}Bow names and because this is what IRIX calls it.
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long. Prompted by deraadt@ long ago.
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pick the right clock if the PCI bus the I/O board is on degrades to 33MHz.
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This is needed for the addition of further suspend/resume actions.
Okay deraadt@, marco@.
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lines. (This is done only to make dmesg look nice)
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on PIC; no functional change.
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of com0 and com2-4.
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the stack. this lets disklabels work on non-sgivol disks.
ok miod
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instead of two 32 bit halves, as the supposedly `upper 32 bits' register
ignores writes; makes interrupt on PIC route correctly.
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xbow''; while there report vendor and product id of unknow xbow chips.
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foo bricks (they differ by having PCI-X bridges instead of PCI bridges
but are otherwise built the same)
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but we only care about the first for matching, so don't bother listing the
second one in xbowdevs, and fix the description.
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registers to be programmed correctly.
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OK miod@
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