summaryrefslogtreecommitdiff
path: root/sys/arch
AgeCommit message (Collapse)Author
2014-04-05qla and qle are working well enough, so just delete use of isp. don'tTheo de Raadt
even comment the lines.
2014-04-04Second step of the R4000 EOP errata WAR: when pmap invalidates a page whichMiod Vallat
is currently being covered by the wired TLB entries, flush them, so that, if the process' pc is still running in a vulnerable page, the WAR will reapply immediately and fault the next page.
2014-04-04If the PDC_COPROC call fails, and we are running on a PA 1.1 system, assumeMiod Vallat
the usual 1.1 coprocessor mask, instead of using zero and having every userland process dying with signal 4. The circumstances under which this call fails are unclear and could be tied to specific PROM version (I have tried overzealous stack alignment and other tricks, to no avail). Interestingly enough, the 715/75 system which hits this problem, only triggers it when booting from disk, and never when booting from network. This diff is an ugly bandaid until the problem is better understood. Or maybe it is not worth investigating, seeing that Linux hardcodes the coprocessor mask and never issues PDC_COPROC calls; I wonder what HP/UX does. In my tree for over 18 months; "Looks like a nice hack" deraadt@ 715/75 system provided by Sebastiaan Indesteege, thanks!
2014-04-04It seems that, when the on-board USB controller is an ALI M5237 USB and itsMiod Vallat
interrupt is routed through the ISA PIC, the interrupt is edge-triggered (despite PCI interrupts being level-triggered). Attempt to recognize this and correctly setup the PIC ELCR register to `edge'. This allows ES40 systems (and maybe others, but apparently all the other alpha systems with on-board M5237 correctly route its interrupt as a PCI interrupt) to reliably boot multiuser without suffering from USB interrupt storms (this is especially noticeable when using glass console which, unlike serial console, does not trigger other interrupts to give other devices a chance to run). However, this is not enough yet to allow for proper USB device usage; your mileage may vary. Tested by bluhm@ and me. Putting it early in the release cycle so that regressions on other systems, if any, can hopefully get noticed soon enough.
2014-04-04let device_register match scsi devices to anything hanging off aDavid Gwynne
scsibus. this lets path drivers get matched instead of just sd(4). ask mpath to maybe swap a path with a disk via mpath. ok deraadt@
2014-04-03Do not keep the EOP check bits in PGF_PRESERVE.Miod Vallat
2014-04-03enable hdsDavid Gwynne
2014-04-03More uvm_extern.h cleanup.Martin Pieuchot
2014-04-03Use <uvm/uvm_extern.h> if it's enough.Martin Pieuchot
2014-04-03Moar <uvm/uvm.h> -> <uvm/uvm_extern.h> love.Martin Pieuchot
2014-04-02enable hdsTheo de Raadt
2014-04-02enable mpathTheo de Raadt
2014-04-01Remove the almost unused abstraction around "struct firmware" and useMartin Pieuchot
instead a single function ppc_mem_regions() required by the ppc pmap. ok kettenis@
2014-04-01Remove the almost unused abstraction around "struct firmware" and useMartin Pieuchot
instead a single function ppc_mem_regions() required by the ppc pmap. ok kettenis@
2014-04-01More <uvm/uvm.h> -> <uvm/uvm_extern.h> cleaning.Martin Pieuchot
ok kettenis@, deraadt@
2014-03-31Use extent_alloc_with_descr(9) and add a mutex to protect the extent.Mark Kettenis
This should make bus_dmamap_load(9) and bus_dmamap_unload(9) "mpsafe". As a bonus this gets rid of a potential memory allocation in the IO path. ok miod@
2014-03-31Due the virtually indexed nature of the L1 instruction cache on most mipsMiod Vallat
processors, every time a new text page is mapped in a pmap, the L1 I$ is flushed for the va spanned by this page. Since we map pages of our binaries upon demand, as they get faulted in, but uvm_fault() tries to map the few neighbour pages, this can end up in a bunch of pmap_enter() calls in a row, for executable mappings. If the L1 I$ is small enough, this can cause the whole L1 I$ cache to be flushed several times. Change pmap_enter() to postpone these flushes by only registering the pending flushes, and have pmap_update() perform them. The cpu-specific cache code can then optimize this to avoid unnecessary operations. Tested on R4000SC, R4600SC, R5000SC, RM7000, R10000 with 4KB and 16KB page sizes (coherent and non-coherent designs), and Loongson 2F by mikeb@ and me. Should not affect anything on Octeon since there is no way to flush a subset of I$ anyway.
2014-03-31Including <uvm/uvm_extern.h> is enough, no need for <uvm/uvm.h> or more.Martin Pieuchot
2014-03-31Change the order of operations during a suspend/resume cycle andMartin Pieuchot
call bufq_quiesce() after executing the DVACT_QUIESCE handlers. This should be safe since no disk nor controller drivers have such handler but it will allow us to detach sd(4) devices attached to a USB bus. Another benefit pointed out by kettenis@ is that drivers that need to read a firmware from the disk should be able to do it at resume time in a DVACT_WAKEUP handler. ok kettenis@, deraadt@
2014-03-31give up on isp, and only use ql[wae]Theo de Raadt
Be a bit cynical about firmware fitting, of course.. ok jmatthew
2014-03-30Eliminates struct pcred by moving the real and saved ugids intoPhilip Guenther
struct ucred; struct process then directly links to the ucred Based on a discussion at c2k10 or so before noting that FreeBSD and NetBSD did this too. ok matthew@
2014-03-30Close the kernel fd before attempting to load /etc/random.seed, and reopen itMiod Vallat
afterwards, for some prom misbehave if the network interface is opened twice; repairs boot.net operation on at least SS5 PROM v2.21; found the hard way by sebastia@. Crank boot version; verified not to hurt disk boot.
2014-03-30Drop isp(4) to make the kernel fit again.Mark Kettenis
ok deraadt@
2014-03-29Update the loongson codebase to recognize the so-called `EFI-like' interfaceMiod Vallat
supposedly provided by newer PMON firmware (on Loongson 2Gq and Loongson 3A systems).
2014-03-29It's been a quarter century: we can assume volatile is present with that name.Philip Guenther
ok dlg@ mpi@ deraadt@
2014-03-29Do not play with the xmapmode register, for its layout seems to differ betweenMiod Vallat
board revisions < 4 (found on Indigo) and >= 4 (found on Indy and Indigo2). Paint the cursor as an inverted glyph, instead of exchanging bg and fg colours (matching the current practice on other frame buffers). Speed-up overlapping copy operations by attempting to perform them in larger chunks whenever possible; this speeds up console jump scrolling.
2014-03-28Add commented out entries for xhci(4).Brad Smith
ok mpi@
2014-03-28enable mpath plus sym and rdac on some archs so we can learn about whatDavid Gwynne
the effects will be. sgi will follow after i fix some known fallout first.
2014-03-27Remove dependency from wscons_machdep upon bonito. Instead of hardcoding bonitoMiod Vallat
as the northbridge, have the per-platform early setup code register functions providing access to the PCI configuration space, for the wscons code to walk the PCI space in search of a graphics board. No functional change yet.
2014-03-27Make sure the HIBERNATE pages get reserved regardless of the memory layout.Miod Vallat
2014-03-27Increase VM_PHYSSEG_MAX, necessary for systems with non-contiguous memoryMiod Vallat
(such as 2E and 3A systems).
2014-03-27{fix,add} comments.Miod Vallat
2014-03-27Add commented out entries for xhci(4).Brad Smith
ok mpi@
2014-03-27Program the colormap correctly; gives us proper shade of blue and highlighting.Miod Vallat
Add a simple screen burner accessop.
2014-03-27replace x86_atomic_cas_things with atomic_cas_foo equivalents.David Gwynne
ok kettenis@
2014-03-26Increase max data size. 32G is the new 640K.Ted Unangst
Using this much memory may have negative side effects, but at least now you have the option. Here's some rope; have fun. maybe ok a few people.
2014-03-26Service R4[04]00SC-specific virtual coherency exceptions directly from theMiod Vallat
lowest bowels of the exception handling code, rather than in trap(). They won't get recorded in the trap history, but there is a measurable speedup. No change for non-CPU_R4000 kernels.
2014-03-26No need to include <sys/lock.h> when only <sys/rwlock.h> is needed,Martin Pieuchot
so remove the former and include the latter instead of pulling it in <dev/pci/agpvar.h>. This header already requires various other types anyway. While here remove unneeded headers.
2014-03-26Move p_emul and p_sigcode from proc to process.Philip Guenther
Tweak the handling of ktrace EMUL when changing ktracing: only generate one per process (not one per thread) and pass the correct proc pointer down to the VFS layer. Permit generating of NAMI and CSW records inside ktrace(2) itself. ok deraadt@ millert@
2014-03-25the memory constraints are correct, so we dont need volatile to provideDavid Gwynne
extra restrictions on ordering.
2014-03-25the memory constraints are correct on the MD_SWAPIO bits, so we dont needDavid Gwynne
the extra restrictions that __volatile provides on the __asm statements.
2014-03-24Only need to call tlb_probe() once per pair, instead of once per page.Miod Vallat
2014-03-24Make sure tlb_probe() reads the probe result before reenabling interruptsMiod Vallat
(egads!). While there, remove leftover instructions from an early flavour of tlb_update_indexed(), which crept in by accident.
2014-03-23Unbreak after last commit.Miod Vallat
2014-03-23Initialize additional BATs (IBAT4-IBAT7 and DBAT4-IBAT7). The rb600 firmwareMark Kettenis
has these enabled and this leads to memory corruption that (surprisingly) only shows up when running PIE.
2014-03-23Repair R5000SC and R4600SC external L2 cache setup, broken in previousMiod Vallat
revision.
2014-03-22Move p_sigacts from struct proc to struct process.Philip Guenther
testing help mpi@
2014-03-22Second draft of my attempt to workaround the infamous R4000 end-of-page errata,Miod Vallat
affecting R4000 processors revision 2.x and below (found on most R4000 Indigo and a few R4000 Indy). Since this errata gets triggered by TLB misses when the code flow crosses a page boundary, this code attempts to identify code pages prone to trigger the errata, and force the next page to be mapped for at least as long as the current pc lies in the troublesome page, by creating wiring extra TLB entries. These entries get recycled in a lazy-but-aggressive-enough way, either because of context switches, or because of further tlb exceptions reaching trap(). The errata workaround code is only compiled on R4000-capable kernels (i.e. sgi GENERIC-IP22 and nothing else), and only enabled on affected processors (i.e. not on R4000 revision 3, or on R4400). There is still room for improvemnt in unlucky cases, but in this simple enough incarnation, this allows my R4000 2.2 Indigo to finally reliably boot multiuser, even though both /sbin/init and /bin/sh contain code pages which can trigger the errata.
2014-03-22Shuffle tlblo-related defines, to better show which bits are software only,Miod Vallat
and which bits end up in the actual tlb registers. On non-R8000 kernels, shrink the actual physical address bits to add a new software bit, PG_SP (for `special'), which will be used shortly. This halves the physical memory addressable by non-MIPS_PTE64 kernels, which should not be a problem anyway.
2014-03-21Rename db_inst_type() into classify_insn() and make that function availableMiod Vallat
outside of ddb. It will be used by regular kernel code shortly.
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-23 11:17:02 +0000