Age | Commit message (Collapse) | Author |
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ever ran on, and it's unlikely to ever be implemented, so remove it.
ok jsg@
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few users to pci_mapreg_info().
ok jsg@
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ok deraadt@ miod@ krw@
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ok visa@
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feedback and ok jmc@ miod, ok millert@
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ok miod@ who tested on Ultra 5
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ok kettenis@ patrick@
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and -mbranch-protection=bti. So turn off the BTI protection in ramdisk
kernels for now.
ok deraadt@, miod@, phessler@
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ok miod@ kettenis@
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Pointed out by miod@, patrick@
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ok kettenis@
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ok miod@
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Since r1.76 "Get rid of pmap_map_early()" the FDT was mapped read-only,
but CRYPTO softraid code writes it to zero out the key.
Found and tested by me; explanation and fix from kettenis.
OK kettenis
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feature introduced in Armv8.5. This provides "head-CFI" to complement
the "tail-CFI" provided by retguard. Unfortunately most arm64 machines
don't support this feature yet. But Apple M2 does support it and it
seems to work there.
ok deraadt@
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ok deraadt@
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requested by and ok deraadt@
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feedback kettenis@ ok miod@
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ok miod@ kettenis@
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except alpha. This will put the stack at a random location in the upper
1/4th of the userland virtual address space providing up to 26 additional
bits of randomness in the address. Skip alpha for now since it currently
puts the stack at a (for a 64-bit architecture) very low address. Skip
32-bit architectures for now as well since those have a much smaller
virtual address space and we need more time to figure out what a safe
amount of extra randomizations is. These architectures will continue to
use a mildly randomized stack address through the existing stackgap random
mechanism. We will revisit this after 7.3 is released.
This should make it harder for an attacker to find the stack.
ok deraadt@, miod@
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ok miod
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ok miod@
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The addition of HZ to sys/kernel.h in v1.26 overrides the default
definition of HZ in sh/clock.c, changing landisk from HZ=64 to HZ=100.
Explicitly set HZ=64 in the GENERIC and RAMDISK config(8) files to can
change it from 100 back to 64.
Not sure if this is the best thing, but it does fix the problem.
Problem confirmed by, and fix tested by, miod@.
ok miod@
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(and RK3588). This is a PIPE PHY with support for PCIe, SATA, USB3, SGMII
and QSGMII. For now only PCIe, SATA and USB3 support are implemented.
SATA support has not been tested.
Also add the refernce clocks needed by the PHYs to rkclock(4).
ok mlarkin@
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build yet.
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ok patrick@
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dlg has a Dell Wyse 3040 with
cpu0: Intel(R) Atom(TM) x5-Z8350 CPU @ 1.44GHz, 480.02 MHz, 06-4c-04
cpu0: mwait min=64, max=64, C-substates=0.2.0.0.0.0.3.3, IBE
which hangs soon after the login prompt with MP kernels
This is a hardware bug described in:
Intel Atom Z8000 Processor Series Specification Update
Document Number: 332067-012
"CHT45 Processor May Not Wake From C6 or Deeper Sleep State"
tested by dlg@, ok guenther@
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No longer limit the ifq size to a low number, increase the slots on the
DMA Ring a bit and abstract the VNET buffer size into a define.
Enqueue packets on the ring but mark the initial packet ready at the end.
This way the other ldom is not able to rush ahead and overconsume packets.
The dring indexes are passed between ldoms and can get out of sync with
causes the TX ring to stall.
Tested by myself and jan@
OK kettenis@ jan@ kn@
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The apic timer mode, mask, and divisor are set during lapic_timer_trigger().
We don't need to reset them when rearming the timer. On physical hardware
the difference is too small to measure, but skipping two apic writes may be
a bit faster when we're running in a VM.
Bochs also likes to log when the apic divisor is changed:
38569516308i[APIC0 ] set timer divide factor to 1
38569517335i[APIC0 ] set timer divide factor to 1
38569518042i[APIC0 ] set timer divide factor to 1
[...]
With this change, Bochs is a lot less noisy.
Idea from mlarkin@.
ok mlarkin@
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ok miod@ millert@
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deprecated more than 25 years ago and removed more than 20.
From Crystal Kolipe, thanks!
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ok miod@
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ok kettenis@ jmatthew@
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This fixes the IPL calculations in mpic_calc_mask() in the presence
of IPL_MPSAFE interrupts such as mvneta(4).
ok patrick@ kettenis@ dlg@
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