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2022-10-15ansiJonathan Gray
2022-10-15ansiJonathan Gray
2022-10-14Pass boot device information from bootloader to kernel.Kenji Aoyama
This brings the default root device is the same one of the kernel specified by bootloader, rather than NVRAM setting, like other architectures. "looks good to me" miod@, tested on LUNA-88K2 and nono (LUNA-88K capable emulator) by me.
2022-10-14No point in luna88k setting D_VENDOR since all actual uses areKenneth R Westerback
inside #ifdef SUN_CYLCHECK or #ifdef SUN_AAT0 blocks in disklabel(8), neither of which are defined for luna88k. ok miod@
2022-10-13Properly implement disestablishing LPI interrupts. Fixes a crash when usingMark Kettenis
virtio(4) in combination with agintc(4). ok jsg@, patrick@
2022-10-13Implement support for MBIs. MBIs are message based interrupts that can beMark Kettenis
used as an alternative implementation for MSIs on hardware that doesn't implement an ITS (or where the ITS is broken such as on the Rochchip RK3566 SoC). Based on an earlier WIP diff from patrick@; I just cleaned it up a bit. ok patrick@
2022-10-12Extend struct todr_chip_handle with a todr_quality member. This allows usMark Kettenis
to assign a quality to RTC implementation and pick the "best" RTC if a system has multiple RTCs (or multiple interfaces to an RTC). This allows us to prefer a battery-backed I2C RTC over an RTC that is part of the SoC which is only running of the SoC is powered. It also allows us to work around issues with firmware RTC interfaces that may lie to us or even crash the system. This change makes sure the todr_quality member of the struct is always initialized. In most cases the quality will be set to zero; further adjustments of the quality for specific subsystems/architectures will follow. ok cheloha@, patrick@
2022-10-12use correct type with sizeofJonathan Gray
ok miod@ kettenis@
2022-10-12Remove powerpc left-oversKlemens Nanni
There since the powerpc -> macppc move/rename. KERN_AS usage disappeared in commit 5b7db11d478192c5908038bb1345e7d51cc35c8e Author: rahnds <rahnds@openbsd.org> Date: Mon May 5 16:47:15 1997 +0000 only build one version of the libraries. REAL_VIRT usage disappeared in commit 08e027d6bb9ca863bfc44a1aa6957ff3a242e2f4 Author: rahnds <rahnds@openbsd.org> Date: Thu Apr 27 12:36:29 2000 +0000 Fixes to xcoff bootloader to allow it to execute and load kernels for OpenBSD. Make agrees that these are defined but not used: $ make -p | grep -e KERN_AS -e REAL_VIRT KERN_AS = library REAL_VIRT = -v $ make -C ofwboot -p | grep -e KERN_AS -e REAL_VIRT KERN_AS = library REAL_VIRT = -v No object change. Feedback OK miod
2022-10-12Fix -Wreturn-typeKlemens Nanni
OK miod
2022-10-11Give checkdisklabel() a new parameter supplying the dev_t of theKenneth R Westerback
device whose disklabel is being checked. Within checkdisklabel() use this information to discover a device name iff (sic) the label is an obsolete version. Use the name to generate a meaningful warning message asking the user to rewrite the disklabel and thus promote it to the current version. Suggested by, feedback from and ok deraadt@
2022-10-10add references to 10h 12h revision guidesJonathan Gray
2022-10-07Add mimmutable(2) system call which locks the permissions (PROT_*) ofTheo de Raadt
memory mappings so they cannot be changed by a later mmap(), mprotect(), or munmap(), which will error with EPERM instead. ok kettenis
2022-10-06Build CRC calc/static block decode tables when needed to fix netbootKlemens Nanni
The last libz update broke sparc64's ofwboot.net on at least T4-2 machines running OpenBoot 4.38.16 as bootblocks grew too big for OBP to load: # size ofwboot.net.* 60684 596 2472 63752 f908 ofwboot.net.71 71340 596 2472 74408 122a8 ofwboot.net.snap {0} ok boot net Boot device: /virtual-devices@100/channel-devices@200/network@0 File and args: TFTP: Transfer timed out As suggested by tb, adapt b7dd453d18bbd69c3a22e9c7e44e83163348942a to make OBP load and execute ofwboot.net over TFTP again on at least T4-2 and T5220 where ofwboot off disk keeps loading and both bootblocks boot plain and gzipped kernels before. Overall size is now smaller that 7.1 release: -current 71340 596 2472 74408 122a8 ofwboot.net/obj/ofwboot.net 119580 532 2512 122624 1df00 ofwboot/obj/ofwboot 71140 532 2472 74144 121a0 ofwbootfd/obj/ofwbootfd -current with -DDYNAMIC_CRC_TABLE -DBUILDFIXED 59788 608 15040 75436 126ac ofwboot.net/obj/ofwboot.net 108028 544 15080 123652 1e304 ofwboot/obj/ofwboot 59588 544 15040 75172 125a4 ofwbootfd/obj/ofwbootfd happy kettenis OK tb
2022-10-04On CPUs that support the Data Independent Timing feature, enable this featureMark Kettenis
by default in both the kernel and userland. At this point, this feature has only been seen on Apple's CPU cores, where turning it on has no measurable impact on performance. Turning this feature on should help to mitigate timing side-channel attacks. ok deraadt@, beck@
2022-10-04Add a few more PSTATE bits.Mark Kettenis
ok deraadt@
2022-10-03Reorganize the EFI code a bit. Move the efi.h header from dev/acpi toMark Kettenis
dev/efi and rename the arm64 efi.c to efi_machdep.c, preparing the way for MI EFI code and an amd64 implementation of EFI runtime support. ok deraadt@, mlarkin@
2022-10-02Fetch vendor and product IDs from the keyboard/touchpad controller.Mark Kettenis
To be used in a future diff to handle machines with touchbar a bit better. ok robert@
2022-09-24add SH-B0 0x00000f50 socket 940 family 0Fh OpteronJonathan Gray
we already had SH-B0 0x00000f40 socket 754 family 0Fh Athlon 64 SH-B0 is part of amd64_errata_set8[]. Used for: Errata 89: Potential Deadlock With Locked Transactions ok deraadt@
2022-09-23Delete unused variables originally come from mvme88k.Kenji Aoyama
2022-09-23only call printf the first time amd64_errata() is calledJonathan Gray
it may later be used from a resume path when we don't want to print same change as amd64 amd64errata.c 1.11 by robert ok robert@ deraadt@
2022-09-22use the always serializing RDTSCP instruction in tsc and usertc if availableRobert Nagy
tweaks from cheloha@; ok deraadt@, sthen@, cheloha@
2022-09-22Call amd64_errata() from cpu_fix_msrs() instead of identifycpu() so thatRobert Nagy
on resume, the errata is re-applied. In addition make amd64_errata() print the information about the applied errata only once for the first CPU. input from jsg@ and deraadt@, ok deraadt@
2022-09-20Split out handling of cpu family specific MSRs from cpu_init_msrs()Robert Nagy
to a separate function that gets called after identifycpu() so that we have the required information to handle the correct MSRs for each cpu. Additionally, move the handling of the DE_CFG_SERIALIZE_LFENCE and IA32_DEBUG_INTERFACE_LOCK MSRs out of identifycpu() to the new function so that they get set again after a suspend/resume cycle as well, which in fixes TSC sync failures. discussed with and input from deraadt@, mlarkin@
2022-09-20remove HY_D1_G34R1 enum value and just use HY_D1Jonathan Gray
HY-D1 C32r1 (0x00100f81) and HY-D1 G34r1 (0x00100f91) have the same errata and multiple cpuid values can map to a single enum value.
2022-09-18Define PMU_ADB_CMD and PMU_INT_ACKGeorge Koehler
Taking these definitions from NetBSD's pm_direct.h; most PMU_* commands have the same names in the BSDs and Linux. ok miod@ kettenis@
2022-09-18tsc: make tsc_report_test_results() less noisy without TSC_DEBUGScott Soule Cheloha
By default, just say "tsc: cpu0/cpuN: sync test failed". If you want more information you need to recompile with TSC_DEBUG set. While here, disable TSC_DEBUG. "sure" deraadt@
2022-09-16move most of the key combination translation code out of ukbd(4)Robert Nagy
to hidkbd so that it can be re-used by apldc(4) and aplhidev(4) as well this also adds support for apple fn key combinations to aplhidev(4) ok miod@
2022-09-15tsc: configure LFENCE to serialize dispatch before testing TSC syncScott Soule Cheloha
On AMD CPUs, LFENCE does not serialize instruction dispatch until MSR C001_1029[1] is properly configured. We do this in identifycpu(); see amd64/identcpu.c,v 1.103. The upshot is that the first TSC synchronization test is currently invalid on most AMD CPUs because the LFENCE in the test loop does not ensure that the AP loads the BP's latest TSC value before executing RDTSC. So the synchronization test is yielding false positives on AMD CPUs where the TSCs are actually synchronized. The simplest fix is to wait until after the secondary CPU runs identifycpu() in cpu_hatch() to test TSC synchronization. Moving the TSC sync test after CPU identification means that we can remove the CPUID() calls from tsc.c: the CPU feature flags are set in identifycpu() so we no longer need to test for IA32_TSC_ADJUST support by hand. While we are at it, we should also pass the correct cpu_info pointer to tsc_test_sync_bp(). It was unused before, so the bug was harmless, but we definitely need the BP's cpu_info pointer, not the AP's pointer. Unfortunately, this change does not fix the TSC sync problems we've been seeing on e.g. dv@'s and jmc@'s Ryzen 5 machines. Hopefully the problem on those machines is buggy firmware and not another architectural misunderstanding on my part. Prompted by robert@. Problem diagnosed by brynet@. With input from robert@, brynet@, and deraadt@. Tested by robert@, brynet@, dv@, phessler@, and jmc@. ok robert@ brynet@ sthen@
2022-09-15Add support for Apple fn key combinations. Based on Apple fn key handlingTobias Heider
in ukbd(4). ok miod@
2022-09-15recognise Neoverse V2 (Demeter)Jonathan Gray
2022-09-13Split out the code that collects data from acpiac(4), acpibat(4) andMark Kettenis
acpisbs(4) for apm(4) and hook it up to the arm64 version of apm(4) on systems with ACPI. ok kn@
2022-09-12Enable acpiac(4) and acpibat(4).Mark Kettenis
ok deraadt@
2022-09-12Store mod/ref flags using md pg_flags values rather than a specific field inMiod Vallat
vm_page_md, which allows this struct to shrink a bit.
2022-09-12Store mod/ref flags using md pg_flags values rather than a specific field inMiod Vallat
vm_page_md, which allows this struct to shrink a bit.
2022-09-12Drop orphaned pv_flags values.Miod Vallat
2022-09-11Add wsmux(4) such that systems with multiple keyboards work in bsd.rd.Mark Kettenis
ok deraadt@, mpi@
2022-09-11On smmu(4) instances without coherent page table walk we need to make surePatrick Wildt
changes to the page tables are made visible, as needed on the Lenovo x13s.
2022-09-11Make an attempt at taking over existing streams on Qualcomm machines. SomePatrick Wildt
of the stream mappings on the Lenovo x13s match on a single stream id, and others use a mask to match on multiple stream ids. For now we only care about the single ones, which is enough to capture e.g. the xhci(4) nodes.
2022-09-10Remove pmap_collect() when a no-op, define __HAVE_PMAP_COLLECT otherwise.Miod Vallat
Use that define to shunt uvm_swapout_threads(), which is a noop when pmap_collect() does nothing. ok mpi@
2022-09-10amd64, i386: lapic_initclocks: install i8254 before lapic_startclock()Scott Soule Cheloha
In the future, the clock interrupt code will need a working timecounter to do its job. In lapic_initclocks(), call i8254_inittimecounter_simple() before lapic_startclock(). The i8254 may be be a piece of junk, but one timecounter is better than none.
2022-09-09Recognize Qualcomm Krys 400 series cores.Mark Kettenis
ok jsg@
2022-09-08The SC7180 (snapdragon 7c) needs the SMMU quirk as well.Mark Kettenis
It seems reasonable that SC8180X/XP needs the quirk too, so preemtively add these to the list as well. ok patrick@
2022-09-08Remove old debug code knobs, wrong comments, and unused pv entry flags.Miod Vallat
ok kettenis@
2022-09-08Rename global ifnet TAILQKlemens Nanni
Naming the list like the struct itself makes for awful grepping. Call the global variable "ifnetlist" from now on. There used to be kvm(3) consumers in base picking up this symbol, but those have long been converted to other interfaces. A few potential ports users remain, same deal as sys/net/if_var.h r1.116 "Remove struct ifnet's unused if_switchport member": they get bumped. Previous users pointed out by deraadt OK bluhm
2022-09-08Remove vm_page_md fields which were only needed for pre-v7 arm ports.Miod Vallat
2022-09-08riscv64: cpu_initclocks: install tb_timecounter before cpu_startclock()Scott Soule Cheloha
In the future, the clock interrupt code will need a real timecounter to work correctly. Nudge the tc_init(9) call for tb_timecounter up before cpu_startclock().
2022-09-08macppc: cpu_initclocks: install tb_timecounter before cpu_startclock()Scott Soule Cheloha
In the future, the clock interrupt code will need a real timecounter to work correctly. Nudge the tc_init(9) call for tb_timecounter up before cpu_startclock().
2022-09-07vmm(4): allow reading MSR_TSC on Intel hosts.Dave Voutila
Add's MSR_TSC to the read bitmap for msr access. This was added to AMD/SVM in Feb 2020, but never added to Intel VMX. Some guests use rdmsr instead of rdtsc, so this prevents a #GP exception. ok mlarkin@
2022-09-07On the Lenovo X13s the named components don't have the single mappingPatrick Wildt
flag set, which we so far had expected to be there. This is allowed by the IORT spec. In that case simply make use of the first mapping if there is a single one. With feedback from and ok kettenis@
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-12 18:50:55 +0000