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so mpi(4) gets removed from the floppy.
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Corrects an off-by-one error that results in EPT pte's not being
removed properly.
ok mlarkin@
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ok kn@
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ok mlarkin@, deraadt@
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If an interrupt-generating device does not have an interrupt-parent
property, its interrupt parent is assumed to be its devicetree
parent.
Implement this aspect of the spec in the same way as Linux does by not
just looking at the immediate parent but keep on walking up the tree
until we hit a node with an "interrupt-controller" property or a node
that has an "interrupt-parent" property.
similar diff as committed for arm64 a couple of days ago
ok jca@
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If an interrupt-generating device does not have an interrupt-parent
property, its interrupt parent is assumed to be its devicetree
parent.
Implement this aspect of the spec in the same way as Linux does by not
just looking at the immediate parent but keep on walking up the tree
until we hit a node with an "interrupt-controller" property or a node
that has an "interrupt-parent" property.
same diff as committed for arm64 yesterday
ok patrick@
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If an interrupt-generating device does not have an interrupt-parent
property, its interrupt parent is assumed to be its devicetree
parent.
Implement this aspect of the spec in the same way as Linux does by not
just looking at the immediate parent but keep on walking up the tree
until we hit a node with an "interrupt-controller" property or a node
that has an "interrupt-parent" property.
ok patrick@
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various Intel SoCs. The driver takes care of calling the AML methods
needed to enter low power idle states during suspend-to-idle (S0i).
The driver also implements some debug code that prints the residency of
various power states in dmesg. Based on some earlier code by jcs@
ok jcs@
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like the others.
Nudged, test, and ok deraadt@
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ok kettenis@
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This lets me boot the Samsung Galaxy Book4 Edge in DT mode with ufshci(4),
based on a WIP DTB file.
ok kettenis@
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Until now the kernel did panic during early boot because we couldn't
respond to the battery requests sent to the 0xa1 "bus". This (dummy)
driver registers a 0xa1 region space very early, and responds with a
static zero value to satisfy the battery requests on 0xa1, which let us
boot successfully to multi-user.
In the future this machine should be operated in FDT mode, and an improved
AML parsing interface might make this workaround obsolete also for RAMDISK.
Help and OK kettenis@, deraadt@
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CPU features.
ok naddy@
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us from trying to put devices into the D3 power state which some hardware
doesn't appreciate.
ok ratchov@, deraadt@
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restores the FPU registers (running in userland). And add an
".arch_extension nofp" afterwards such that the remaining kernel code
can't touch the FPU.
Needed to build with clang18
ok jsg@
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According to the AMD64 Architecture Programmer's Manual volume 2
the intercept SVM_INTERCEPT_INVLPGA needs to be set in vmcb.intercept1
(vector 3, offest 00Ch) instead of intercept2 (vector 4, offset
010h). SVM_INTERCEPT_INVLPGA is bit 26, so before vcpu_reset_regs_svm()
was actually setting an intercept for CR10, which does not exist.
from hshoexer@; OK mlarkin@
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otherwise clang 18 errors when inline assembly uses floating point
registers with nofp in -march
ok kettenis@
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registers from userland and set HWCAP_CPUID. This will allow detection
of features to be introduced into the architecture in the future without
allocating new HWCAP_xxx or HWCAP2_xxx bits. We provide the same
sanitized view of the CPU ID registers as is currently available through
sysctl(2).
Note that this introduces an unconditional read of ID_AA64MMFR2_EL1. This
is known to cause problems on older versions of QEMU. If this turns out
to be a problem in cases where updating QEMU is not an option, we'll have
to implement a workaround.
Also note that since we don't emulate the CPU ID registers on older core,
this means that microarchitectural optimizations keyed of reads of MIDR_EL1
are not possible on OpenBSD. I don't think that is a real problem.
ok jca@
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vmm(4) only supports using nested paging on Intel or AMD and no
longer supports HLAT or shadow paging.
ok mlarkin@
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Actually determine the C-bit position if we are running as a guest
with SEV enabled. Configure pg_crypt, pg_frame and pg_lgframe
accordingly, using the physical address bit reduction provided by
cpuid.
from hshoexer@; OK mlarkin@
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values and the feature bits that we recognize.
ok naddy@, jca@
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Input from miod@ and gkoehler@, tests & ok gkoehler@
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Input from miod@ and gkoehler@, tests & ok gkoehler@
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the stack utilization ends up near the the deep end of the stack where,
retcleans are useful. tested for a while in snaps
ok bluhm
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sysclt(2) and ID register access emulation can share the variables.
ok jca@
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The spice^Wkernel must flow^Wbuild.
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Designed to let userland peek at AT_HWCAP and AT_HWCAP2 using an already
existing interface coming from FreeBSD. Headers bits were snatched from
there. Input & ok kettenis@
libc bump and sets sync will follow soon
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Since vmm handles nested page faults in the vcpu run loop, trying
to avoid trips back to userland, it's possible for the thread to
move host cpus. vmm(4) already updates some local cpu state when
this happens, but also needs to update the host cr3 in the vmcs to
allow vmx to restore the proper cr3 value on the next vm exit.
Additionally, we should be flushing the ept cache on the new cpu.
If the single context flush is available, use that instead of the
global flush.
ok mlarkin@
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ok patrick@, deraadt@
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machines. The shipped hardware containing ath11k and ath12k WiFi cards all
need to have 32-bit DMA constraints enforced.
ok kettenis@
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Similar to the NX-bit apply the C-bit to the PTEs built by locore0.
Right now, pg_crypt is initialized to 0, so nothing will change.
from hshoexer@; OK mlarkin@
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idle power usage of the Vivobook S15 by almost 50%.
ok patrick@
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efi(4) such that we can access EFI variables through ioctls on /dev/efi.
ok patrick@
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Forgot `cvs add` and sys/dev/vmm/vmm.h changes.
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Makes as much of the core of vmd mi, pushing x86-isms into separate
compilation units. Adds build logic for arm64, but no emulation
yet. (You can build vmd, but it won't have a vmm device to connect
to.)
Some more cleanup probably needed around interrupt controller
abstraction, but that can come as we implement more than the i8259.
ok mlarkin@
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The C-bit in a page table entry is used by a SEV guest to specify,
which pages are to be encrypted and which not. The latter is needed
to share pages with the hypervisor for virtio(4).
The actual position of the C-bit within a PTE is CPU implementation
dependend and needs to be determined dynamically at system boot.
The position of the C-bit also determines the actual size of page
frame mask. This will be provided by a separate change.
To be able to use the same kernel as both host and guest, the C-bit
is provided as variable similar to the NX-bit. Same holds for the
page frame masks.
Right now, pg_crypt is set to 0, pg_frame an pg_lgframe to PG_FRAME
and PG_LGFRAME respectively. Thus the kernel works as a host system
same as before.
Also introduce a PMAP_NOCRYPT flag. A guest will use this with
busdma to establish unencrypted mappings that can be shared with
the hypervisor.
from hshoexer@; OK mlarkin@
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ok mlarkin
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To prepare for mi/md splitting vmd, need to fixup the dev/vmm/vmm.h
mi header. Move the vm_run_params struct and clean up the includes
in vmd.
"sure", mlarkin@
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when merging changes from FreeBSD in i386 rev 1.10
db_Esca5 was added but not used
ok mlarkin@
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ok kettenis@, mlarkin@, miod@, claudio@
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avoids a division by 0 when up'ing the non-working cnmac2 on er-poe
feedback from visa@:
"The cnmac2 link is connected to a discrete Ethernet switch chip on the
PoE, and this link does not carry RGMII in-band PHY status. If the code
were to support such hardware designs in the future, something like this
patch would be needed."
this diff from miod@, same diff from visa@ in 2017
(cf https://marc.info/?l=openbsd-bugs&m=151017517115440&w=2)
ok visa@
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ok kettenis@
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ok mlarkin@ kettenis@
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