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batch = pdemask == sva && sva + ~PDE_MASK + 1 <= eva;
with something that's a little bit easier to read.
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ok miod@
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whether removing holes or parts of them is allowed or not.
Only allow hole removal in uvmspace_free(), when tearing the vmspace down.
ok art@
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range covered by the next PDE and not somewhere in the middle. The old could
have skipped over some valid PTE's causing them to stay behind in the pmap.
Since we would not flush the cache for those pages either this could also
cause memory corruption when dirty cache lines would be written back to
memory at a later stage.
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ok kettenis
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ok kettenis@
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ok miod@
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ok miod@
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ok miod@
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PCI ROM into account, if any.
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their ROM if they have any.
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caller deal with this; this really makes the PMAP_CANFAIL logic work.
ok kettenis@
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backed pages.
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it's at routine+0; do not search for the previous routine in the symbol
table. This fixes tracebacks when the fault occurs on the first instruction
of a routine.
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- do not use a stinking extent to track bus_space_map allocations, but
directly map in XKPHYS instead. What are 64 bit address spaces good for
if we still need to use TLB for that?
- provide proper resource management extents to the MI pci code, so that,
in turn, the cardbus code can reuse them instead of providing their own.
- use the whole 4GB address space window for PCI I/O resources, just
because we can.
- make sure no device can get assigned address zero in I/O space, because
this address triggers a PCI error.
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accordingly.
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reported in dmesg.
While there, silence the spurious interrupt warning logic if, at the time
it is triggered, there are really no hardware interrupts pending; this can
happen if serial interrupts gets processed e.g. at splx() before the
hardware interrupt routine has a change to run.
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memory leak plug from drahn@
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class systems. Tested on O2 and Origin 200 with wi@pcmcia and xl@cardbus,
using a Ricoh 5C475-based cbb(4) board.
acx@cardbus doesn't work reliably yet, so your mileage may vary until more
bugs are fixed.
Thanks to matthieu@ for lending me some cardbus devices for testing.
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of the bus_space_tag_t it contains; an upcoming implementation will need
to know the rbus_tag_t for which it works at this point.
All callers updated accordingly; no functional change intended.
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logic to be chipset dependent; no functional change yet.
ok kettenis@
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The firmware messes up I/O BARs, so whack those back to 0, such that the MI
PCI code initializes on an as-needed basis.
ok miod@
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ARCS, except for IOC3 devices (which might be our console). This allows
us to build resource accounting extents to pass the MI code (for more magic).
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work on systems with xbridge.
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where the common part to all bus_dmamap_load*() functions is implemented in
in an internal load_buffer routine.
This allows the xbridge-specific dma code to only provide this function,
instead of three; and this also brings us a working bus_dmamap_load_uio()
on all supported sgi machines, which in turns make crpyto(4) devices really
work. Tested with hifn(4).
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which crept in the previous commit.
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ok sthen
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help & ok miod@
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per-pci_chipset_t function to perform actual resource allocation.
Add the necessary bits to macepcibr(4), and enable ppb(4) on O2 kernels now.
Joint effort with kettenis@
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configuration register; this allows the driver to select ultra speed, which
this particular hardware supports.
From Linux, ok kettenis@
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- Stop hmestop() from fiddling with the flags directly and
calls mii_down() instead.
From Brad, tested by nick@.
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Not tested on hardware, but at least compiles now.
problem pointed out by Sylvestre Gallon
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bridge initialization if necessary; enable ppb on IP27 and IP30 kernels.
With feedback from kettenis@; macepcibr to gain the same functionality soon.
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GENERIC and SUN4M kernels.
ok miod@
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the sun4m iommu. Bits and pieces from NetBSD, with some additional tweaks
and a bus_dmamap_load_mbuf() implementation from myself.
ok miod@
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ok miod@
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memory initialization. This reduces memory test and initialization time
from a "in soviet russia, memory test you" time of over 2 minutes for 1GB
on Origin 200, to a more reasonable 12 seconds (and on a Fuel with 2GB,
time goes down from 6 seconds to under a second).
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More architectures hopefully to follow.
ok kettenis@
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