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2022-08-29static const, not const staticJonathan Gray
c99 6.11.5: "The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature." ok miod@ tb@
2022-08-29static inline, not inline staticJonathan Gray
c99 6.11.5: "The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature." ok guenther@
2022-08-29use ansi volatile keyword, not __volatile__Jonathan Gray
ok miod@ guenther@
2022-08-29use ansi volatile keyword, not __volatileJonathan Gray
ok miod@ guenther@
2022-08-29Support full GICD SPI interrupt count for REG32/REG16.Dale Rahn
This enables SPI support for interrupts on X13s. ok jsg@
2022-08-27Add power button support.Mark Kettenis
ok tobhe@
2022-08-27Provide ENTRY_NB() for i386Theo Buehler
ok guenther
2022-08-25amd64/lapic.c: remove unused extern prototype for tsc_delay()Scott Soule Cheloha
2022-08-25The "Avalanche" performance cores on Apple's M2 SoC have more than 16Mark Kettenis
P-states. As a result the layout of the "state" register changed. Make the driver handle that. Also make sure we use the correct lowest state in case the lowest frequency of the performance cores is different from the lowest frequency of the efficiency cores. ok tobhe@
2022-08-25amd64, i386: use delay_init() instead of writing delay_func by handScott Soule Cheloha
Now that we have delay_init(), use it in all the places where we currently set delay_func by hand. lapic_delay() is great: 3000. hv_delay() is needed before we set up lapic_delay() on Hyper-V guests: 4000. tsc_delay() is better than lapic_delay() and (probably?) hv_delay(): 5000. We may bump hv_delay's quality value up over that of tsc_delay() in a future patch. It's a little ambiguous whether hv_delay() causes a VM exit. Idea and patch from jsg@. With tons of input, research and advice from jsg@. Link: https://marc.info/?l=openbsd-tech&m=166053729104923&w=2 ok mlarkin@ jsg@
2022-08-25amd64, i386: add delay_init(): basic delay(9) implementation managementScott Soule Cheloha
Because the clock situation on x86 and amd64 is a terminal clusterfuck, there are many different ways to delay(9). We need a rudimentary mechanism for gracefully switching to progressively better delay(9) implementations as they become available during boot without riddling the code with ifdefs and function pointer comparisons. This patch adds delay_init() to both amd64 and i386. If the quality value passed to delay_init() exceeds the quality value of the current delay_func, delay_init() changes delay_func to the given function pointer and updates the quality value. Both platforms start with delay_func set to i8254_delay() and a quality value of zero: all other delay(9) implementations are preferable. Idea and patch provided by jsg@. With tons of input, research, and advice from jsg@. Link: https://marc.info/?l=openbsd-tech&m=166053729104923&w=2 ok mlarkin@ jsg@
2022-08-25No need for wsmux in this kernel configuration; ok visa@Miod Vallat
2022-08-24Add DIT CPU feature.Mark Kettenis
ok beck@
2022-08-24Add missing licence, from nonaka@netbsd.orgMiod Vallat
2022-08-24Build libsa with NO_NET as we don't need any of the network-related code in it.Miod Vallat
2022-08-24Force compilation to fail in case of implicit function declaration.Miod Vallat
2022-08-24Add prototype declarations for a bunch of functions.Miod Vallat
2022-08-23Added NFS client support to RAMDISK kernel as the same as other platforms.Kenji Aoyama
Tested by me.
2022-08-23Recognize the cores on Apple's M2 SoC.Mark Kettenis
ok jsg@, tobhe@, deraadt@
2022-08-22Get number of interrupt cells from device tree instead of guessing basedTobias Heider
on version. Fixes M2 Macbook Air 2022 which reports version 2 but only uses 3 cells. ok kettenis@
2022-08-22remove locore.s bzero and use libkern bzero on i386Jonathan Gray
libkern bzero doesn't have the 486 path but is otherwise the same ok mlarkin@ deraadt@
2022-08-22remove extern for cpu var removed in 2015Jonathan Gray
ok daniel@
2022-08-22remove cpu var from i386; removed from amd64 in 2015Jonathan Gray
ok daniel@
2022-08-22mips64, octeon, loonson: trigger deferred clock interrupts from splx(9)Scott Soule Cheloha
As with powerpc, powerpc64, and riscv64, on mips64 platforms we need to isolate the clock interrupt schedule from the MD clock interrupt code. To do this, we need to stop deferring clock interrupt work until the next tick and instead defer the work until we logically unmask the clock interrupt from splx(9). Add a boolean (ci_clock_deferred) to the cpu_info struct to note whether we need to trigger the clock interrupt by hand, and then do so from splx(9) by calling md_triggerclock(). Currently md_triggerclock is only ever set to cp0_trigger_int5(). The routine takes great care to ensure that INT5 has fired or will fire before returning. There are some loongson machines that use glxclk instead of CP0. They can be switched to use CP0 later. With input and advice from visa@ and miod@. Compiled and extensively tested by visa@ and miod@ on various octeon and loongson machines. No issues seen on octeon machines. miod@ saw some odd things on loongsoon, but suggests that all issues are probably unrelated to this patch. Link: https://marc.info/?l=openbsd-tech&m=165929192702632&w=2 ok visa@, miod@
2022-08-20drop detection code for Cyrix CPUs older than the Cyrix M2Daniel Dickman
The 486DLC is a 486-class CPU which we no longer support on i386. The 6x86 (also known as the M1) did not support CPUID by default[*] so extra support code is needed to differentiate between these early Cyrix processors in order to apply some errata that the M1 needs. However the 6x86 doesn't implement the RDTSC instruction so we can remove support code for this CPU at this point. Cyrix implemented RDTSC in the 6x86MX (also known as the M2). So this is likely the earliest Cyrix CPU that we can support on i386. We keep the support code in "cyrix6x86_cpu_setup" because early 6x86MX CPUs would continue to benefit from this fixup code. [*]: CPUID can be enabled on the Cyrix 6x86 by setting bit 7 of CCR4 ok mlarkin@, jsg@
2022-08-20remove Cyrix 486DLC register defines from amd64Daniel Dickman
Cyrix CPUs don't support amd64. These defines were probably carried over from i386 accidentally when the amd64 code was first imported. ok mlarkin@, jsg@
2022-08-18repair printing of cpu class after machdep.c 1.652Jonathan Gray
ok daniel@ mlarkin@
2022-08-18Move recomputation of hz and stathz from glk to glkclk, lets a kernel withMiod Vallat
glkclk disabled keep correct values of those. NFC
2022-08-17Mention support for booting off RAID 1CKlemens Nanni
2022-08-17Fix vldc(4) event filtersVisa Hankala
Indicate non-activeness when the device is not ready for reading or writing. This should make the event filters behave more like the old poll code. "makes sense to me" mpi@
2022-08-17No more disklabel -B.Miod Vallat
2022-08-15unifdef KDBJonathan Gray
2022-08-15Add softraid(4) RAID 1C boot supportKlemens Nanni
This is the arm64 adaptation of stsp's (commitid: p55cmsVoEH0fRg77) "add support for booting from RAID 1C softraid(4) volumes on amd64". Tell the boot loader to decrypt 1C like C volumes and check the number of disks in 1C like in 1C volumes -- no new code rquired. Tested on SolidRun CEX7 OK stsp NB: While kernel and boot loader support root on softraid on arm64, installboot(8) does not, i.e. default installations still require manual disk preparation for now.
2022-08-15drop detection code for 386sx/386dx CPUsDaniel Dickman
OpenBSD/i386 doesn't actually support running on 386sx or 386dx CPUs so we don't need to test whether we're running on one of these CPUs anymore. The 486 (which was launched in 1989) added a few new features over the 386: - an alignment check flag in EFLAGS - 3 new userland instructions: bswap / cmpxchg / xadd - 3 new kernel mode instructions: invd / wbinvd / invlpg - new bits in CR0 (386 CPUs did not support ring0 write protection) - new bits in CR3 In this diff, we remove the code that checks for the alignment check flag as we've only supported Pentium (or newer) CPUs for some time. The rest of the diff is about updating comments related to pre-486 CPUs. 2 files under arch/amd64 are updated to keep them in sync with the arch/i386 updates. ok mlarkin@, jsg@; tweak from miod@
2022-08-13avoid uninitialised var when boot_unit has an unexpected valueJonathan Gray
tested by and ok aoyama@
2022-08-12Crank amd64 boot loader version numbers for softraid(4) RAID 1C boot support.Stefan Sperling
2022-08-12add support for booting from RAID 1C softraid(4) volumes on amd64Stefan Sperling
Only boot-loader changes are needed. Both installboot(8) and the kernel already do what is required to make this work. ok kn@ Tested: biosboot on vmm: kn, stsp biosboot and efiboot on server hardware: stsp
2022-08-12Make sure we don't pass uninitialized siginfo values to trapsignal(); fromMiod Vallat
clang via jsg@, ok jsg@
2022-08-12Fix to work 1bpp Xorg server again on 1bpp framebuffer hardware.Kenji Aoyama
Recent xenocara wsfb driver can treat LUNA's framebuffer "offset", but it requires one more page by mmap() when we use offset. Noticed and tested on nono emulator with 1bpp setting.
2022-08-12use string literal for format stringJonathan Gray
ok deraadt@ miod@
2022-08-12use string literal for format stringJonathan Gray
ok miod@
2022-08-12amd64: simplify TSC synchronization testingScott Soule Cheloha
Computing a per-CPU TSC skew value is error-prone, especially on multisocket machines and VMs. My best guess is that larger latencies appear to the current skew measurement test as TSC desync, and so the TSC is demoted to a kernel timecounter on these machines or marked non-monotonic. This patch eliminates per-CPU TSC skew values. Instead of trying to measure and correct for TSC desync we only try to detect desync, which is less error-prone. This approach should allow a wider variety of machines to use the TSC as a timecounter when running OpenBSD. In the new sync test, both CPUs repeatedly try to detect whether their TSC is trailing the other CPU's TSC. The upside to this approach is that it yields no false positives. The downside to this approach is that it takes more time than the current skew measurement test. Each test round takes 1ms, and we run up to two rounds per CPU, so this patch slows boot down by 2ms per AP. If any CPU fails the sync test, the TSC is marked non-monotonic and a different timecounter is activated. The TC_USER flag remains intact. There is no middle ground where we fall back to only using the TSC in the kernel. Before running the test, we check for the IA32_TSC_ADJUST register and reset it if necessary. This is a trivial way to work around firmware bugs that desync the TSC before we reach the kernel. Unfortunately, at the moment this register appears to only be available on Intel processors. I cannot find an equivalent but differently-named MSR for AMD processors. Because there is no per-CPU skew value, there is also no concept of TSC drift anymore. Miscellaneous notes: - This patch adds a new timecounter utility function, tc_reset_quality(). Used after sync test failure to mark the TSC non-monotonic. - I have left TSC_DEBUG enabled for now. Unsure if we should leave it enabled for release or not. If we disable it we no longer run the sync test after failing it once. Running the test even after failure provides information about the desync on every CPU. - Taking 1ms per test round is fairly conservative. We can experiment with and discuss shorter test rounds. My main goal with a relatively long test round is ensuring VMs actually run the test. It would be bad if a hypervisor interrupted the test for so long that it concealed desync. - The use of two test rounds is mostly a diagnostic tool: it would be very strange if a CPU passed the first round but failed the second. If we ever saw this in the wild it would indicate something odd. - Most of the desync seen in test reports is on Ryzen CPUs. I believe, but cannot prove, that this is due to a widespread firmware bug on AMD motherboards. Hopefully AMD and/or the downstream vendors fix it. - Fixing TSC desync by writing the TSC directly with WRMSR is very difficult. The TSC is a moving target incrementing very quickly and compensating for WRMSR overhead is non-trivial. We can experiment with this, but my confidence is low that we can make it work reliably. Prompted by deraadt@ and kettenis@ in 2021. Shepherded along by deraadt@ throughout. Reprompted by Yuichiro Naito several times. With input from Yuichiro Naito, naddy@, sthen@, dv@, and deraadt@. Tested by florian@, gnezdo@, sthen@, Josh Rickmar, dv@, Mohamed Aslan, Hrvoje Popovski, Yuichiro Naito, semarie@, mlarkin@, asou@, jmatthew@, Renato Aguiar, and Timo Myyra. Patch v1: https://marc.info/?l=openbsd-tech&m=164330092208035&w=2 Patch v2: https://marc.info/?l=openbsd-tech&m=164558519712957&w=2 Patch v3: https://marc.info/?l=openbsd-tech&m=165698681018991&w=2 Patch v4: https://marc.info/?l=openbsd-tech&m=165835507113680&w=2 Patch v5: https://marc.info/?l=openbsd-tech&m=165923705118770&w=2 "just commit it" deraadt@
2022-08-11powerpc64: cpu_initclocks: do tc_init(9) before cpu_startclock()Scott Soule Cheloha
In the future, the clock interrupt will need a working timecounter to accurately reschedule itself. Move tc_init(9) up before cpu_startclock(). kettenis@ notes several other platforms need this same change. Maybe we can do the rest all at once. Tested by kettenis@. Link: https://marc.info/?l=openbsd-tech&m=165343754512382&w=2 ok kettenis@
2022-08-11Don't yet configure smmu(4) on Qualcomm SoCs as used on the Lenovo x13sPatrick Wildt
as it is still not ready for runtime use and probably needs further quirks. Discussed with deraadt@
2022-08-10On the Qualcomm SoC as implemented on the Lenovo x13s the BIOS alreadyPatrick Wildt
configures and makes use of the SMMU. We need to keep those mappings alive as otherwise the machine will die and reboot. Unfortunately we cannot simply set those domains to bypass, as when we set a domain to bypass it is actually set to fault. Instead reserve a domain and set it to disabled, which behaves the same as if we used a bypass mapping. With feedback from kettenis@
2022-08-10Also attach spdmem on Gdium.Miod Vallat
2022-08-10Pass the "good random" flag from the bootblocks to the kernel when applicable.Miod Vallat
2022-08-10Add iic at glxpcib, to get spdmem to attach on 2F-based systems.Miod Vallat
2022-08-10Remove alpha kernel code to process userland misaligned accesses, and theMiod Vallat
machdep.unaligned_* sysctl to control its behaviour. Such code made sense more than 20 years ago where a lot of code was not 64-bit clean, but this is no longer the case those days. ok jsg@ millert@ deraadt@
2022-08-10match other archs use %s for version printfJonathan Gray
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