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2017-02-13whitespace tweak. no functional change.David Gwynne
2017-02-12Split up fork1():Philip Guenther
- FORK_THREAD handling is a totally separate function, thread_fork(), that is only used by sys___tfork() and which loses the flags, func, arg, and newprocp parameters and gains tcb parameter to guarantee the new thread's TCB is set before the creating thread returns - fork1() loses its stack and tidptr parameters Common bits factor out: - struct proc allocation and initialization moves to thread_new() - maxthread handling moves to fork_check_maxthread() - setting the new thread running moves to fork_thread_start() The MD cpu_fork() function swaps its unused stacksize parameter for a tcb parameter. luna88k testing by aoyama@, alpha testing by dlg@ ok mpi@
2017-02-11Always leave one free slot in the Tx ring to avoid ambiguity with ringVisa Hankala
head and tail in the interrupt handler. This fixes an old bug that causes a Tx stall when Tx ring gets full.
2017-02-11Simplify ifq_deq_{begin,rollback,commit} sequence to ifq_dequeue.Visa Hankala
2017-02-11Let MP-safe interrupt handlers run without the kernel lock on sgi.Visa Hankala
OK miod@
2017-02-10Unbreak 'config -p'.Martin Pieuchot
ok tb@, jca@
2017-02-08Now pcexmem(4) and pcexio(4) are attached at cbus(4), we do not need toKenji Aoyama
include "pcex.h" here.
2017-02-08Pass the physical address to the end of symbols to the kernel. FromPatrick Wildt
armv7 we inherited the mechanism to manually modify the kernel symbol table to change the value of esym. We don't use this, but instead use the virtual address that is passed to the kernel. This change makes us only work on and hand out physical addresses. Bump the efiboot version to make this ABI change more visible.
2017-02-08Retry BS->ExitBootServices() if it fails, like on amd64. Also we needPatrick Wildt
to make sure to pass the current mapkey to prove EFI that we know the current memory map and its constraints. Otherwise EFI can choose to only partially exit until we pass the correct key. As we already use the memory map to allocate memory for the kernel, split the previous function into one simply retrieving the table and another one who uses the map to allocate memory. At some point it would be nice to actually pass the table to the kernel since its data is more reliable than the FDT only. While there, sync a bit of style with the amd64 version.
2017-02-08In exec_elf.c: expand ELFNAME(), ELFNAME2(), and ELFNAMEEND() exceptPhilip Guenther
leaving out the size, so that ELFNAME2(exec,makecmds) becomes exec_elf_makecmds instead of exec_elf{32,64}_makecmds and then delete the ELFNAME2() and ELFNAMEEND() macros. Move the prototypes for functions local to exec_elf.c to there from exec_elf.h. Simplify the SMALL_KERNEL conditionals around the ELF coredump code. Change exec_conf.c to use the size-generic names and macros Remove exec_elf{32,64}.c and just build exec_elf.c; delete the _KERN_DO_ELF and _KERN_DO_ELF64 #defines. ok jca@, encouragement from deraadt@ and tom@
2017-02-08Retry BS->ExitBootServices() if it fails.YASUOKA Masahiko
Reported by Ryan, pulse.purge at gmail.com
2017-02-07Since the instruction cache does not in any way snoop the data cachePatrick Wildt
we need to make sure to clean the data and invalidate the instruction cache upon entering a page with pmap_enter(). Since it is possible that pmap_enter() does not directly enter the page, we need to do the same dance in the pmap fault fixup code. Every new writeable mapping or write removes a page's flag to mark it unflushed. The next time pmap_enter() is called or a fault happens on that VA, it has to be flushed and invalidated again. This was heavily discussed with Dale Rahn. On the Pine64 and Raspberry Pi 3 we have been very lucky to not run into any cache issues, especially with the instruction cache. The AMD Seattle seems to be a different kind of beast where we actually have to care about these things. This finally brings the machine into userland.
2017-02-07For consistency sake, apply the inner shareable attribute to the bootstrapPatrick Wildt
pagetables as well. Also replace the number for write-back with a proper define.
2017-02-07The default frequency we chose for the generic timer does not always ringPatrick Wildt
true. Instead, unless overwritten by the device tree, we should ask the generic timer for its frequency. This fixes time on my AMD Seattle and should improve time management on QEMU as well.
2017-02-07There are 1023 possible values for the interrupts, but our masks limitPatrick Wildt
these currently to 255. Thus making it impossible to use higher IRQs than that. The AMD Seattle SoC though seems to provide 448 IRQs, which is kind of out of bounds, so raise them to the proper values. This makes interrupts work on that machine.
2017-02-07Reduce the per-packet allocation costs for crypto operations (cryptop)Patrick Wildt
by pre-allocating two cryptodesc objects and storing them in an array instead of a linked list. If more than two cryptodesc objects are required use mallocarray to fetch them. Adapt the drivers to the new API. This change results in one pool-get per ESP packet instead of three. It also simplifies softraid crypto where more cryptodesc objects are allocated than used. From, with and ok markus@, ok bluhm@ "looks sane" mpi@
2017-02-06Move cache and tlb flush functions, which were mostly inline assembly,Patrick Wildt
into separate functions. This makes them reusable from other parts in the kernel. Assembly and header are taken from FreeBSD, but modified to fit our requirements and with some unnecessary stuff removed. While there remove micro optimization for uniprocessor kernels.
2017-02-06Mark ehci_intr() as MP-safe on octeon.Visa Hankala
OK mpi@
2017-02-06Sync a comment with i386.Martin Pieuchot
2017-02-06Implement Dynamic Profiling, a ddb(4) based & gprof compatible kernelMartin Pieuchot
profiling framework, for i386. Code patching is used to enable probes when entering functions. The probes will call a mcount()-like function to match the behavior of a GPROF kernel. A new sysctl knob, ddb.profile, need to be set to 1 in securelevel 0 to be able to use this feature. ok jasper@, guenther@, mlarkin@
2017-02-06Change the pmap_pmap_pool ipl from IPL_VM to IPL_NONE. Matches theJonathan Gray
other archs. ok patrick@
2017-02-06patrick@ tells me this is mostly mine tooDavid Gwynne
2017-02-06add a license for the code in here, all of which i seem to have written.David Gwynne
this has been pointed out to me by a couple of people now.
2017-02-06When determining whether or not to hatch into PAE mode, use the cpu_paeMike Larkin
flag variable instead of checking some pointer assignment made earlier in pae_bootstrap. ok guenther
2017-02-05_dmamem_alloc_range() stores physical addresses in the segments, soPatrick Wildt
upon free don't try to convert it from virtual to physical again.
2017-02-05Ask for a generic armv8-a encoding rather than one based on and tunedJonathan Gray
for cortex-a57. ok patrick@
2017-02-05Add implementation for intr_barrier(9).Patrick Wildt
2017-02-05Add the necessary PCI header to be able to compile PCI drivers. BasedPatrick Wildt
on the octeon one.
2017-02-05Since turning of the MMU in the beginning of the kernel removesPatrick Wildt
the caches' contents, we lose data about the freshly copied and created kernel. This leads to bootup failures. Make sure to clean the caches to make sure that the data is in memory before we turn off the MMU.
2017-02-05Implement another pagetable level for bootstrapping machines that havePatrick Wildt
their memory mapped above 39 bits of address space. Since our pmap is configured to use a 3 level pagetable userland we need to reconfigure the size back to 39 bits as soon are in virtual address space and have finished using the FDT via the 1:1 map.
2017-02-05As far as we understood the architecture reference manual it shouldPatrick Wildt
only need a data cache write-back to PoU (Point of Unification) to make changes to the pagetables visible. Interestingly enough, this does not seem to work on the AMD hardware. Instead we need to flush to PoC (Point of Coherence), which essentially means flush to memory. Surprisingly even FreeBSD flushes their pagetable changes to PoC, and they have done that since the code was first imported. Until we find out whether this is a software bug or just completely expected, switch us to flushing to PoC as well. This makes my AMD machine behave.
2017-02-05Add option PCIVERBOSE.Patrick Wildt
Prompted by jsg@
2017-02-04In reality our kernel does not need to be aligned at a 256M boundary,Patrick Wildt
but simply at 2M boundary. This might have been a requirement from armv7, but it's not true for arm64. This also helps reduce memory holes below the kernel.
2017-02-04Read the data cache size instead of hardcoding some value. We mightPatrick Wildt
want to start caching that value somewhere though.
2017-02-04A bit of code and comment cleanup.Patrick Wildt
2017-02-04Remove gdb waitcount debug code and dummy print.Patrick Wildt
2017-02-04Implement atomic_{set,clear}bits_int and membars for arm64.Jonathan Gray
With feedback from Dale Rahn, ok patrick@.
2017-02-03Implement a helper that creates an L0 pagetable entry pointing toPatrick Wildt
a L1 pagetable. Needed for machines that need 4 level pagetables on bootup. From FreeBSD
2017-02-03whitespace fixesPatrick Wildt
2017-02-03Set the context id and counter offset to a known value. Enable accessPatrick Wildt
to the physical timers at EL1. From FreeBSD
2017-02-03Use PAGE_SHIFT instead of encoding the number.Patrick Wildt
From FreeBSD
2017-02-03Cleanup pagetable creation code in preparation for adding another levelPatrick Wildt
of pagetables to bootstrap machines with physical memory mapped outside of a 39 bits address space. From FreeBSD
2017-02-03ARM64 has an 48-bit physical address space, so bump PTE_RPGN to reflectPatrick Wildt
it. Otherwise we might truncate physical addresses.
2017-02-03Don't use PTE_RPGN to mask away the lower page bits from a virtualPatrick Wildt
address. PTE_RPGN only returns the physical bits that can be used, thus truncating virtual addresses, specifically in kernel address space.
2017-02-03Explicitly ask EFI to allocate the page we picked out to lay ourPatrick Wildt
kernel in, and not just use some memory address that we found in the table.
2017-01-26Disable pgt(4) and acx(4) on sparc64. The kernel has grown too large.Stefan Sperling
Unbreaks the build and allows GENERIC.MP to boot again on T5220. I am quite sure the zero users of these old wireless cards on sparc64 will be much happier with a ral(4) or athn(4) card instead. ok otto@
2017-01-26The only difference between armv7 and arm64 fdt virtio attachments is anJonathan Gray
uneeded include. Remove the include and move to MI fdt directory.
2017-01-25Build amd64 kernels with -ffreestanding. Synchronize the arm64 and armv7Mark Kettenis
kernel makefiles, that are using -ffreestanding already, with the amd64 one. Other architectures will follow later. ok jca@, visa@
2017-01-25Setjmp and longjmp save/restore 13 registers in a label_t struct,Patrick Wildt
not only 11 registers.
2017-01-25Setjmp should return zero, while longjmp should return nonzero inPatrick Wildt
kernel. Since those are only used by ddb, guard them with DDB.
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