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2021-10-06Change sendsig() interface so that the MD code does not need to accessClaudio Jeker
data from struct process anymore. This changes how siginfo and onstack are accessed and make sendsig() more MP friendly. With and OK semarie@ OK kettenis@
2021-10-06Add openbsd,dma-constraint property to /chosen node on armv7Visa Hankala
On the Zynq-7000, the DMA constraint has to be adjusted because many bus masters are unable to access the lowest part of RAM. OK patrick@ kettenis@
2021-10-05cleanup conf.c, and bring in wd(4) supportTheo de Raadt
ok kettenis
2021-10-05wd(4) device node support was missing, add it.Theo de Raadt
2021-10-04grow i386 media for new realtek firmwaresTheo de Raadt
2021-09-25Fix a possible race condition in spc_msgin().Kenji Aoyama
This comes from NetBSD:sys/dev/ic/mb89352.c fix by tsutsui: http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/dev/ic/mb89352.c.diff?r1=1.57&r2=1.58&f=h Tested on LUNA-88K2 by me.
2021-09-25Add $OpenBSD$ keyword and correct spelling.Kenji Aoyama
2021-09-25Add gpiocharger(4) for arm64Klemens Nanni
This driver provides support for battery chargers connected to GPIO pins, such as those found on the Pinebook Pro. OK kettenis
2021-09-25Add gpioleds(4) for arm64Klemens Nanni
This driver provides support for LEDs connected to GPIO pins, such as those found on the Pinebook Pro. OK kettenis
2021-09-24Fix two bugs in m88k fcmp{,u} emulation.Kenji Aoyama
- Use of goto will skip zeroing of 88110-specific comparison bits (bitn 12-17) in some cases. (Move their zeroing closer to the point of their computation.) - Computing of the "in interval" bits should not be performed when the S2 operand is negative. Spotted by Tetsuya Isaki (nono project), suggested diff and description from Miod Vallat. Tested on the real hardware by Isaki and me.
2021-09-19Unlock top part of the VM fault handler.Martin Pieuchot
This is possible now that pmap_extract() is serialized with pmap_remove(). ok sthen@, deraadt@
2021-09-17Sync 1bpp initial palette setting with NetBSD/luna68k.Kenji Aoyama
Tested by me on 1bpp framebuffer got recently.
2021-09-14Cleanup some style issues and remove some unused code. In particular,Mark Kettenis
remove the half-finished code to support the SV48 MMU page table layout. Currently there is no hardware that supports that model and I don't expect any hardware that does support it to show up anytime soon. ok mlarkin@
2021-09-14Cleanup some style issues.Mark Kettenis
ok mlarkin@
2021-09-14Make pmap_extract() mpsafe by grabbing the kernel lock for userland pmapsMark Kettenis
while walking the page tables. ok deraadt@
2021-09-14Make pmap_extract() mpsafe by grabbing the kernel lock for userland pmapsMark Kettenis
while walking the page tables. ok mpi@, deraadt@
2021-09-14Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)Jeremie Courreges-Anglas
Modelled after the arm implementation. The first consumer would be __builtin___clear_cache() in libcompiler_rt. Input from kettenis@ and deraadt@, ok kettenis@
2021-09-14Enable cy(4) on amd64.Jan Klemkow
ok deraadt
2021-09-13vmm(4): add limit to number of vcpusDave Voutila
After fixing previous syzbot issues related to lock contention, the reproducer code managed to hit an issue where it can exhaust kernel memory by allocating vcpus. Since each vcpu (regardless if it's SVM or VMX-capable) requires wiring some number of pages of memory, it was possible to starve other parts of the kernel. This change limits the total number of vcpus to 512, a conservative number given vmm(4) only supports single vcpu guests at the moment. ok mlarkin@
2021-09-13Remember to lock user pmap in pmap_extract()Visa Hankala
pmap_extract() has to lock user pmap to prevent concurrent pruning of the page table. The kernel pmap is exempt from this because it uses a fixed page table structure.
2021-09-13Consistently use unsigned long for CPU masks in pmap.c.Visa Hankala
2021-09-13Enable uaq(4) on amd64. Investigations into problems on other platformsJonathan Matthew
are ongoing.
2021-09-11Change the scope of the locking in pmap_extract() to prevent a race betweenMark Kettenis
walking the page tables and another thread calling pmap_remove() that ends up removing a page table page. tested by sthen@ ok deraadt@, mpi@
2021-09-09Adjust for DT binding changes. Add some temporary backwards compatibilityMark Kettenis
code to help making the transition. This will be removed in a few weeks.
2021-09-06Accompany some functions wich are marked inline with the static keywordPatrick Wildt
to make the arm64 kernel link when compiled with -fno-inline. ok kettenis@ mpi@
2021-09-06Serialize access to the global list of pmaps with a mutex.Martin Pieuchot
This prevents possible corruption due to a concurrent access between pmap_growkernel() & pmap_create/pmap_destroy(). Discussed with and ok kettenis@
2021-09-05vmm(4): raise vm pool ipl to IPL_MPFLOORDave Voutila
Similar to the recent change by mpi in revision 1.288, commitid: A4zhVhOoHAIpRGBJ, raise the ipl level of the vm_pool to IPL_MPFLOOR to prevent lock ordering issues. ok mpi@
2021-09-05vmm(4): fix vcpu locking issues reported by syzbotDave Voutila
Syzbot found 3 issues related to the new vcpu lock. This diff adds a write lock to vm_rwregs (needed on VMX as vmread instructions require taking ownership of the vcpu to load the VMCS) and prevents locking the vcpu in vm_run if we fail the cas operation for toggling vcpu state. In the future, we can push the locking in vm_rwregs on AMD SVM systems. The panics in question: panic: rw_enter: vcpulock locking against myself panic: lock (rwlock) vcpulock not locked panic: vcpulock: lock not held Reported-by: syzbot+1dab11e14aa7a159cadf@syzkaller.appspotmail.com Reported-by: syzbot+36244e105daffa1a81b6@syzkaller.appspotmail.com Reported-by: syzbot+c78b5644c7dc3d9b689a@syzkaller.appspotmail.com ok mlarkin@
2021-09-05Introduce dummy pagers for 'special' subsystems using UVM objects.Martin Pieuchot
Some pmaps (x86, hppa) and the buffer cache rely on UVM objects to allocate and manipulate pages. These objects should not be manipulated by uvm_fault() and do not currently require the same locking enforcement. Use the dummy pagers to explicitly document which UVM functions are meant to manipulate UVM objects (uobj) that do not need the upcoming `vmobjlock' and instead still rely on the KERNEL_LOCK(). Tested by many as part of a larger diff. ok kettenis@, beck@
2021-09-04To mitigate against spectre attacks, AMD processors without theAlexander Bluhm
IBRS feature need an lfence instruction after every near ret. Place them after all functions in the kernel which are implemented in assembler. Change the retguard macro so that the end of the lfence instruction is 16-byte aligned now. This prevents that the ret instruction is at the end of a 32-byte boundary. The latter would cause a performance impact on certain Intel processors which have a microcode update to mitigate the jump conditional code erratum. See software techniques for managing speculation on AMD processors revision 9.17.20 mitigation G-5. See Intel mitigations for jump conditional code erratum revision 1.0 november 2019 2.4 software guidance and optimization methods. OK deraadt@ mortimer@
2021-09-04in backtraces, print as many arguments as the function actually hasJasper Lievisse Adriaanse
since amd64 is compiled with -msave-args we have all arguments available to print and there's no reason to limit this to six. discussed with kettenis@
2021-09-03add kprobes provider for dtJasper Lievisse Adriaanse
this allows us to dynamically trace function boundaries with btrace by patching prologues and epilogues with a breakpoint upon which the handler records the data, sends it back to userland for btrace to consume. currently it's hidden behind DDBPROF, and there is still a lot to cleanup and improve, but basic scripts that observe return codes from a probed function work. from Tom Rollet, with various changes by me feedback and ok mpi@
2021-09-03Zap a chatty printfJeremie Courreges-Anglas
ok mlarkin@ kettenis@
2021-09-03It's time to enable smmu(4).Patrick Wildt
ok kettenis@ some time ago
2021-09-03Don't pretend we support PT_STEP on this architecture.Jeremie Courreges-Anglas
The RISC-V doesn't seem to provide hardware support for generic purpose single stepping, and we're not emulating single stepping for riscv64 like we do for alpha or mips64. Hiding PT_STEP makes it possible to run inferior processes with a wip ports/devel/gdb update. ok kettenis@
2021-09-03Enable ptrace(2) support for PT_GETFPREGS/PT_SETFPREGSJeremie Courreges-Anglas
The code is already there, it was unreachable because of this #if 0. ok kettenis@
2021-09-03vmm(4): grab kernel lock before vmspace initDave Voutila
We need the kernel lock before calling some uvm functions. Fixes a panic reported by syzbot. Reported-by: syzbot+dd7a70eaf794705db27e@syzkaller.appspotmail.com ok mlarkin@
2021-09-02trailing whitespaceJasper Lievisse Adriaanse
2021-09-02Fix comment spelling.Patrick Wildt
2021-09-02add aq(4) to amd64 RAMDISK_CD and riscv64 RAMDISKMike Larkin
2021-09-02Fix the TCR_TG0_xxx definitions and add TCR_TG0_4K to the initial settingMark Kettenis
of TCR_EL1 in locore to make clear we use 4K pages for both userland and the kernel. ok patrick@
2021-09-02aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adaptersMike Larkin
Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This driver supports 1Gbps through 10Gbps modes of operation based on the hardware and media/switch capabilities. The initial code was ported from NetBSD, with jmatthew@ finishing up the Tx/Rx ring support and interrupt handler routine. The driver only supports devices using firmware V2. This diff enables aq(4) on riscv64 and amd64, the only platforms where I have tested the driver, but it likely works on other architectures as well.
2021-09-02Initialize mutex to IPL_NONE.Martin Pieuchot
ok kettenis@
2021-09-02rename rw locks to avoid ambiguity and verbosenessDave Voutila
Syzbot might complain about "new" panics, but to help debug a recent report it helps to have unique rw lock names. "sounds good to me" @mlarkin
2021-09-01Use ttopen in tty drivers open functions as ttysleep string, as the others do.Jan Klemkow
ok patrick@
2021-09-01Prevent lock ordering issue by raising ipl level of vcpu_pool to IPL_MPFLOOR.Martin Pieuchot
Reported-by: syzbot+c8905496cd61610f77e2@syzkaller.appspotmail.com ok mlarkin@
2021-09-01Older AMD CPUs that do not support IBRS need an lfence after retAlexander Bluhm
to stop speculation. This seems to be necessary when the branch predictor hits the ret for the first time. In their white paper to mitigate speculation attacks, AMD's retpoline example has an explicit lfence. Adjust our retpoline assembly macro in the kernel. OK guenther@ mortimer@ deraadt@
2021-08-31vmm(4): add ipi for vmclear, unlock kernelDave Voutila
On Intel VMX hosts, when a guest migrates cpus, VMCS state needs to be flushed to physical memory before being reloaded on the new cpu. This diff adds a new ipi to allow a guest resuming on a new cpu to signal to the old that it needs to vmclear. To better surface the potential race conditions, unlock the kernel after handling the ioctl to vmm and simplify the run loops for both vmx and svm. This requires a new vcpu lock. Tested by some on tech@. "go for it" @mlarkin
2021-08-31Only use the i8254 delay code if we are specifically using the i8254 asPatrick Wildt
delay func. Otherwise simply delay for a second to calibrate the LAPIC. Install the lapic delay func only if we were using the i8254 before as delay func. Discussed with the hackroom ok kettenis@
2021-08-31Identify the paravirtual bus earlier, as we need to make sure that we havePatrick Wildt
a working delay func ready before the first occurence of delay(). This is necessary on Hyper-V Gen 2 VMs where we don't use the TSC. Discussed with the hackroom ok kettenis@
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