Age | Commit message (Collapse) | Author |
|
prefetchable and "normal" mmio at the host bridge level we can simply pass
the same extent.
ok patrick@
|
|
ok mpi@
|
|
ok patrick@
|
|
The APM spec defines an APM_UPDATE_TIME event that is meant to cause
the driver to rebase the system's wallclock against the RTC. The
event itself is apparently caused by occasional blackout periods where
interrupts cannot be delivered, which might cause the system to miss a tick.
The problem is that on systems where these events are frequent this
constantly erodes the system wallclock. The RTC is not the greatest
clock in the world so these systems are always playing catch-up.
ntpd(8) is a far better clock corrector than rebasing against the RTC,
so it should be safe to simply ignore the event. We continue to record
the event for userspace listeners, but we do not call inittodr(9) on
receipt of the event.
Linux has ignored the event since v2.6.21:
https://github.com/torvalds/linux/commit/c1d370e167d66b10bca3b602d3740405469383de#diff-d85b9a44da8e5dfb2fb1bcbd304c2a6c
Discovered by jcs@. Discussed a bit with jcs@, tedu@, deraadt@. Fix
tested by jcs@.
"I think we should ignore the event" deraadt@
|
|
allocation service to allocate a block of memory below 16MB such that there
is no risk of overwriting it when the bootloader moves the kernel in place.
It removes the 128k limit that was previously there.
Based on an earlier diff by patrick@
ok mlarkin@
|
|
committing now so this can be worked on in tree
Thanks to the OpenBSD Foundation for sponsoring this work and kettenis@
for helping.
|
|
the RDCL_NO bit of the ARCH_CAPA msr only indicates one of the MDS
subissues is mitigated; only the MDS_NO bit indicates they're all
mitigated.
ok jsg@ mlarkin@
|
|
|
|
|
|
If the CPU has the new VERW behavior than that is used, otherwise
use the proper sequence from Intel's "Deep Dive" doc is used in the
return-to-userspace and enter-VMM-guest paths. The enter-C3-idle
path is not mitigated because it's only a problem when SMT/HT is
enabled: mitigating everything when that's enabled would be a _huge_
set of changes that we see no point in doing.
Update vmm(4) to pass through the MSR bits so that guests can apply
the optimal mitigation.
VMM help and specific feedback from mlarkin@
vendor-portability help from jsg@ and kettenis@
ok kettenis@ mlarkin@ deraadt@ jsg@
|
|
This diff adds support to be able to load a randomly linked kernel VA
(subject to some range restrictions). This change has been in snaps for
a few days without any fallout.
ok deraadt@
|
|
stage does not need execute access, so map the page initially with
read-write protection.
OK miod@
|
|
invalidation is done by mips64 pmap when the branch emulation page is
made executable.
Originally, the pmap_proc_iflush() call was necessary. The instruction
cache invalidation was added in pmap_protect() after the FPU emulation
was introduced.
OK miod@
|
|
From miod@
|
|
'looks good' kettenis@
|
|
Emulate kvm pvclock in vmm(4). Compatible with pvclock(4) in OpenBSD. Linux
does not attach to this (yet).
Fixes by reyk@ and tested extensively by reyk@, tb@ and phessler@
ok mlarkin@ phessler@ reyk@
|
|
|
|
commit to unbreak the build.
from kettenis@
ok drahn@
|
|
cpu_idle_cycle()
ok mpi@ kettenis@
|
|
|
|
Add a first cut of x86 page table walker to vmd(8) and vmm(4). This function is
not used right now but is a building block for future features like HPET, OUTSB
and INSB emulation, nested virtualisation support, etc.
With help from Mike Larkin
ok mlarkin@
|
|
configuration done by TF-A between boards we have to shift the priorities
that we use for both the architected ICC_PMR_EL1 register and the
memory mapped priority registers on the GIC in different ways. Make this
explicit in the code and try to handle all the cases we care about.
This includes QEMU and RK3399 boards that still use the TF-A version
provided by Rockchip.
Seems to make the rockpro64 run stable with a GENERIC kernel.
ok drahn@, patrick@
|
|
|
|
|
|
|
|
Removes some code and files not needed by efi32 and efi64.
ok guenther
|
|
A Type-C controller has multiple tasks. Even though the orientation
of the plug doesn't matter for the user, it matters for the hardware.
To be able to know how to route the SuperSpeed pins you need to know
which way the plug is connected. Also you need to know if you're a
sink/source or device/host. To get the first connection, you toggle
between the modes until you find a connection. In case you see that
a sink is connected, you can turn on USB Vbus to power the sink.
This driver explicitly does not implement USB's Type-C state machine,
but if we get more and more of these controllers it might be worth
doing. Also there's no support for Power Delivery messages yet.
ok kettenis@
|
|
ok kettenis
|
|
Make 2 separate efiboots, one for 32 bit and one for 64 bit to allow
us to remove lots of #ifdef code. Needed to ease the development effort
for random-VA linked kernels
ok tedu, deraadt
|
|
Make 2 separate efiboots, one for 32 bit and one for 64 bit to allow
us to remove lots of #ifdef code. Needed to ease the development effort
for random-VA linked kernels
ok tedu, deraadt
|
|
Separate out files used by both BIOS and EFI boot modes. These files
had many #ifdef EFIBOOT code paths that make it difficult to move forward
with changes needed to support random base VA linked kernels.
ok deraadt@
|
|
There were some exits for instructions that were unhandled and caused the guest
to terminate if it tried to execute them. We now inject a #ud for those. Also
intercept and #ud RDTSCP and INVLPGA instructions.
ok mlarkin@
|
|
OK kettenis@ deraadt@
|
|
|
|
ok deraadt@
|
|
with the ASID format on TLB entry lines.
|
|
ok phessler, deraadt
|
|
a part of the free memory list, terminating it prematurely.
|
|
Make sure that any preceding stores become visible to other CPUs before
setting the AST flag in need_resched() and signotify(). This should
prevent a very unlikely case with inter-CPU ASTs where the receiving
CPU uses stale state.
When clearing the AST flag in ast(), ensure that the clearing store
is performed before any other memory accesses in the AST handler.
Otherwise, there is a slight risk of losing an AST request that gets
posted while the handler is running.
OK guenther@
|
|
The barrier ensures that any lockless state changes become visible
to other CPUs before the IPI is sent. Otherwise, a receiving CPU
might still observe an old state when it processes the interrupt.
OK guenther@
|
|
Make the interrupt and trap return paths check for ASTs with interrupts
disabled. If there is no pending request, interrupts are kept disabled
until return to userspace. This fixes delayed processing of an AST
request that arrives from another CPU after the AST flag has been
checked but before the CPU has finished the return path. The IPI that
follows the setting of the AST flag forces kernel re-entry and recheck
of AST.
Noticed by guenther@
|
|
Pointed out by Jerome Pinot
|
|
Pointed out by Jerome Pinot
|
|
Pointed out by Jerome Pinot
|
|
Pointed out by Jerome Pinot
|
|
Pointed out by Jerome Pinot
|
|
Pointed out by Jerome Pinot
|
|
|
|
random data into the buffer that we feed the kernel.
ok deraadt@, mlarkin@
|
|
region is properly allocated by the firmware.
Move the .bss clearing to locore.S because the section has to be ready
when the stack is taken into use. This additionally makes the
C environment more consistent at the start of mips_init().
|