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AgeCommit message (Collapse)Author
2018-09-12Make pmap_protect(9) actually remove exec permission if the new permissionsMark Kettenis
include PROT_READ but not PROT_EXEC. ok patrick@
2018-09-12Whitespace fixesPhilip Guenther
2018-09-12Now that the pmap is more paranoid about some shootdowns (pmap.c rev 1.119),Philip Guenther
avoid some TLB flushes by not reloading %cr3 when the value isn't changing. original diff by and ok mlarkin@
2018-09-12When shooting pages in the KVA range, all pmaps have the page mapped,Philip Guenther
not just pmap_kernel() and this CPUs pmap. Meanwhile, when mapping another pmap's tables, order the locking so that we don't need IPIs specific to the temp pmap. tested in snaps for a bit ok mlarkin@
2018-09-12Move -Wno-address-of-packed-member to the clang block as well and syncJonathan Gray
armv7 and i386 with amd64. ok guenther@
2018-09-11Put clang-specific options behind conditionals to reduce meta-warningsPhilip Guenther
ok mpi@
2018-09-11Include bnxt in arm64.ccardenas
Tested on mcbin with Broadcom BCM57404 (Dell variant). Ok jmatthew@ and kettenis@
2018-09-11We actually support 39-bit VA's in userland.Mark Kettenis
ok patrick@, jsg@
2018-09-11Add defines for amd microcode msrs which appear to be present since k8Jonathan Gray
though amd only provides public redistributable updates for >= family 10h.
2018-09-09pmap_activate() should match cpu_switchto, so set up ci_{kern,user}_cr3Philip Guenther
if activating for the current thread and meltdown mitigations are in effect. Not clear if it's actually possible to hit the case where this matters, but it's the Right Thing. ok mlarkin@
2018-09-09Simplify pmap_is_curpmap(): %cr3 can never match pm_pdirpa_intel herePhilip Guenther
as this code isn't present in those page tables ok mlarkin@
2018-09-09Calculate automatically the padding necessary for lining up thePhilip Guenther
iretq instruction used when Meltdown mitigation is effect. It got pushed off when an lfence was added in locore.S rev 1.107, resulting in two signals being sent instead of one when iretq faulted, and neither signal had the correct sigcontext info. Update the makefile rule for locore.o to verify that things are correct. ok mlarkin@
2018-09-09Apply retguard to the last asm functions in the arm64 kernel. This completesmortimer
retguard in the kernel and brings the number of useful ROP gadgets at runtime to zero. ok kettenis@
2018-09-08Bump NMBCLUSTERS to a more reasonable 256MB instead of the tiny 4MB.Claudio Jeker
May help ports builders to not run out of memory. Lots of agreement and OK n2k18@
2018-09-07Add retguard macros to cpu_switchto, setjmp, longjmp.mortimer
ok kettenis@
2018-09-06fix whitespaceJonathan Gray
2018-09-05Add defines for dealing with PCID support in cr3Philip Guenther
ok mlarkin@
2018-08-31Move kcov device definitions into <sys/conf.h>.Visa Hankala
OK anton@ deraadt@ kettenis@ mpi@
2018-08-31enable bnxt(4)Jonathan Matthew
2018-08-30Move .dynstr before _edata to fix image size calculation. The PEPatrick Wildt
header contains an image size field that is calculated using the difference between the start of the header and edata. Since we copy out .dynstr into the EFI binary, make sure that .dynstr is before edata so that it's included in the image size. This makes it consistent with efiboot on armv7. ok kettenis@
2018-08-29First pass in bringing i386 in sync with amd64. This does not yet work, but ispd
being committed now so we can work on the rest in-tree. ok mlarkin@
2018-08-29move the todr chip handle into a prtc_softc structureDavid Gwynne
no realy change, this avoid having to allocate the todr struct in attach ok deraadt@
2018-08-28add support for storing the time of day on OPL based machines.David Gwynne
this let's me pull the date back from 2023 to 2018, and have it stay like that after a reboot. ok deraadt@
2018-08-27Add hitemp(4), a driver for the temperature sensors on the HiSilicon Hi3660Mark Kettenis
and Hi3670 SoCs.
2018-08-27Add hiclock(4). Make sure hireset(4) attaches early.Mark Kettenis
2018-08-27move bwfm* at pci? to the wireless sectionJoshua Stein
2018-08-27Enable hireset(4).Mark Kettenis
2018-08-27Add glue for the USB3 controller on the HiKey 970.Mark Kettenis
2018-08-27ompinmux has been replaced by pinctrlJonathan Gray
2018-08-27switch from ompinmux to pinctrlJonathan Gray
ok kettenis@
2018-08-27Enable radeondrm(4). Note that on arm64 we do not yet have a way toMark Kettenis
determine whether radeondrm(4) is the console or not. So leave out the bits that try to make sure the console ends up with drm0/wsdisplay0 that we have on other platforms.
2018-08-26Add pinctrl(4), a generic pin mux driver.Mark Kettenis
ok patrick@
2018-08-26Add plgpio(4), a driver for the ARM PrimeCell GPIO (PL061) peripheral.Mark Kettenis
ok jsg@, patrick@
2018-08-25Add code to print the characteristics of the caches that can be discoveredMark Kettenis
through the CLIDR_EL1 register. ok patrick@
2018-08-25Add GPT support. Mostly copied from amd64.Mark Kettenis
ok krw@
2018-08-25Add umt(4) for USB Windows Precision Touchpad devicesJoshua Stein
Based on imt(4) Rename HIDMT_INPUT_MODE_MT to HIDMT_INPUT_MODE_MT_TOUCHPAD ok deraadt
2018-08-25Define __HAVE_ACPI.Mark Kettenis
ok deraadt@, krw@, jca@
2018-08-25Fix printing of ioapic remapping messages; avoid printing duplicate info.Mark Kettenis
ok deraadt@
2018-08-25Insert new child nodes at the end.Mark Kettenis
ok patrick@
2018-08-25As Intel(TM) cpus are discovered to have more bugs, more workaround MSRsTheo de Raadt
are added. Presence of such MSRs is indicated with a feature flag, which we probe and print at startup for each AP CPU. EFI screen scrolling hasn't gotten faster (yet) and 9600 baud serial console is still the same speed as 1980. Final piece of the puzzle is machines have more cpus, providing more opportunity for screen scrolling and serial fifo's to fill up. The BSP cpu is watching the AP cpus probe and print, but increased latency causes it to exceed a timeout and print "cpuXX: failed messages". Crank that timeout. discussed with kettenis, ok guenther
2018-08-25Don't treat UnicodeChar == 0 as a keyboard input. The same fix wasYASUOKA Masahiko
done on amd64 already. Original diff from Frank Groeneveld ok tb patrick
2018-08-24print cpu family/model/stepping in dmesgJonathan Gray
discussed with deraadt@ bluhm@ and sthen@
2018-08-24Don't treat UnicodeChar == 0 as a keyboard input.YASUOKA Masahiko
This fixes the problem that which prevents typing the passpharase for softraid on boot. It happened at least with some external keyboards on ThinkPad X2{6,8}0. diff from Frank Groeneveld ok tb
2018-08-23Set the pointer to the EFI Runtime Services, otherwise we call intoPatrick Wildt
nowhere. ok kettenis@
2018-08-23port the amd64 code for loading intel microcode on boot to i386Jonathan Gray
ok deraadt@ mlarkin@
2018-08-22Enable uscom(4) where uslcom(4) is already present.Martin Pieuchot
Based on a submisison from Jan Klemkow.
2018-08-22Adding membar_xxx defines to userland.Kenji Aoyama
The src/lib/libc/thread/rthread.c 1.8 change adds #include <sys/atomic.h> in userland code. Current m88k atomic.h contents are inside of #if defined(_KERNEL) guard, then, nothing is defined for userland program. So we need adding some defines to compile it on m88k. The original diff is suggested from Miod Vallat, modified by the advice from mpi@ and kettenis@. ok kettenis@
2018-08-21Perform mitigations for Intel L1TF screwup. There are three options:Theo de Raadt
(1) Future cpus which don't have the bug, (2) cpu's with microcode containing a L1D flush operation, (3) stuffing the L1D cache with fresh data and expiring old content. This stuffing loop is complicated and interesting, no details on the mitigation have been released by Intel so Mike and I studied other systems for inspiration. Replacement algorithm for the L1D is described in the tlbleed paper. We use a 64K PA-linear region filled with trapsleds (in case there is L1D->L1I data movement). The TLBs covering the region are loaded first, because TLB loading apparently flows through the D cache. Before performing vmlaunch or vmresume, the cachelines covering the guest registers are also flushed. with mlarkin, additional testing by pd, handy comments from the kettenis and guenther peanuts
2018-08-21Rework kcov kernel config. Instead of treating kcov as both an option and aanton
pseudo-device, get rid of the option. Enabling kcov now requires the following line to be added to the kernel config: pseudo-device kcov 1 This is how pseudo devices are enabled in general. A side-effect of this change is that dev/kcov.c will no longer be compiled by default. Prodded by deraadt@; ok mpi@ visa@
2018-08-21If a kernel thread was created by a user land system call, the userAlexander Bluhm
land FPU context was saved to proc0. This was an information leak as proc0 is used to initialize the FPU at exec and signal handlers. Never save the FPU to proc0, it has the initialization value. Also check whether the FPU has valid user land state that has to be forked. This bug is a regression from the eager FPU commit. OK guenther@
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