| Age | Commit message (Expand) | Author |
|---|
| 2019-10-27 | Add i.MX5/6 support and enable this driver on armv7(4). | Mark Kettenis |
| 2019-10-23 | Add sxisid(4), a driver to read the on-chip eFuses written by | Mark Kettenis |
| 2019-10-21 | Add sxipwm(4) and pwmbl(4). Thse two drivers together add support for the | Mark Kettenis |
| 2019-10-17 | Avoid including an armv7 MD header. | Mark Kettenis |
| 2019-10-16 | Move sxidog(4) such that we can use it on arm64. | Mark Kettenis |
| 2019-10-13 | Fix whitespace issue spotted by Krystian Lewandowski. | Mark Kettenis |
| 2019-10-13 | Add display brightness hooks. | Mark Kettenis |
| 2019-10-07 | Add moxtet(4), a driver for the Turris Mox modules. For now this | Patrick Wildt |
| 2019-10-07 | Add mvspi(4), a driver for the SPI controller on the | Patrick Wildt |
| 2019-10-07 | Add SPI clocks. | Patrick Wildt |
| 2019-10-07 | Add amliic(4), a driver for the I2C controller found on Amlogic SoCs. | Mark Kettenis |
| 2019-10-07 | Restart the send queue (rather than just clearing OACTIVE) when we've | Jonathan Matthew |
| 2019-10-06 | Add support for i2c clock. | Mark Kettenis |
| 2019-10-06 | Add support for i2c pins. | Mark Kettenis |
| 2019-10-04 | Add support for setting the CPU clock frequencies. This enables DVFS. | Mark Kettenis |
| 2019-09-30 | Add pwmreg(4), a driver that implements a voltage regulator that uses a | Mark Kettenis |
| 2019-09-30 | Add amlpwm(4), a driver for the PWM controller found on various Amlogic SoCs. | Mark Kettenis |
| 2019-09-29 | Fix pasto. | Mark Kettenis |
| 2019-09-29 | Replace dwge(4) with a new driver based on dwxe(4). There are many | Mark Kettenis |
| 2019-09-21 | Register sxits(4) as a thermal sensor with the thermal zone support code. | Mark Kettenis |
| 2019-09-21 | Register sxitemp(4) as a thermal sensor with the thermal zone support code. | Mark Kettenis |
| 2019-09-21 | Implement setting the CPU clock for Allwinner A10/A20 SoCs. | Mark Kettenis |
| 2019-09-20 | Add A20 GMAC clocks. | Mark Kettenis |
| 2019-09-20 | DMA works on the RK3288 as well, so unconditionally enable it. | Mark Kettenis |
| 2019-09-20 | Start using the generic clock code on RK3288 as well by switching over the | Mark Kettenis |
| 2019-09-20 | Add RK3288 GMAC clock. | Mark Kettenis |
| 2019-09-20 | More RK3328 GMAC clock tweaking. | Mark Kettenis |
| 2019-09-19 | Add RK3328 GMAC clocks. | Mark Kettenis |
| 2019-09-16 | Add RK3399 GMAC clock. | Mark Kettenis |
| 2019-09-12 | Prepare for the emac/gmac "phy" property being renamed to "phy-handle" | Jonathan Gray |
| 2019-09-09 | Update the bindings for imxsrc(4), since they changed when they were | Patrick Wildt |
| 2019-09-09 | Attach imxsrc(4) early and raise its priority to make sure it beats | Patrick Wildt |
| 2019-09-08 | Add Allwinner H6 support. | Mark Kettenis |
| 2019-09-07 | Retrieve SFP information using the SFP framework. | Patrick Wildt |
| 2019-09-07 | Add sfp(4), a driver that allows talking to SFPs connected over | Patrick Wildt |
| 2019-09-07 | Register mviic(4) in the I2C framework. | Patrick Wildt |
| 2019-09-06 | missing ; | Theo de Raadt |
| 2019-09-06 | Add mviic(4), a driver to support the I2C controller on the | Patrick Wildt |
| 2019-09-06 | Add I2C clock gates. | Patrick Wildt |
| 2019-09-06 | zero hash bits early in dwxe_iff() | Jonathan Gray |
| 2019-09-05 | Add mvdog(4), a driver to support the watchdog on the Armada 3700 SoC. | Patrick Wildt |
| 2019-09-05 | Add missing RCS Id. | Patrick Wildt |
| 2019-09-05 | Add Allwinner H6 support. | Mark Kettenis |
| 2019-09-03 | Add support for getting the frequency of the CPU clocks. | Mark Kettenis |
| 2019-09-03 | remove unreachable return | Jonathan Gray |
| 2019-09-02 | Implement setting the CPU clock for Allwinner A64 SoCs. | Mark Kettenis |
| 2019-09-02 | Implement setting the CPU clock for Allwinner A64 SoCs. | Mark Kettenis |
| 2019-09-02 | A few more missing bits: power regulators, eMMC power sequencing, | Mark Kettenis |
| 2019-09-02 | Two additional pin configurations. | Mark Kettenis |
| 2019-09-01 | Write to the correct register when setting the output level for a GPIO pin. | Mark Kettenis |
