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2020-11-19Use bus_space_mmap(9) instead of pmap_extract(9) to find out the physicalMark Kettenis
(CPU) address of the device. Pointed out by miod@ ok patrick@
2020-11-17Split imxiic(4) into the FDT-attachment code and the i.MX I2C codePatrick Wildt
in preparation for upcoming ACPI-attachment. ok kettenis@
2020-11-14Add support for the VF610 I2C controller to imxiic(4). It uses itsPatrick Wildt
own clock divisor table and its registers are each a byte apart. The status register is write 1 to clear instead of write 0 to clear, and the enable bit is also inverted. ok kettenis@
2020-11-14Move enabling/disabling the I2C controller and clearing the InterruptPatrick Wildt
Flag into their own functions, since these are the two single pieces of register content that behave differently on the VF610. ok kettenis@
2020-11-14Add 10G media support. This makes the 10G ports on the "single shot" modelMark Kettenis
work. The "double shot" model needs more work (support for "clause 45" PHYs). ok patrick@
2020-11-13Assert reset before configuring the MACs. Otherwise we leave the 10G MACMark Kettenis
in reset which prevents it from working. ok patrick@
2020-11-13To prepare for upcoming VF610 support, access the clk div table usingPatrick Wildt
a pointer in the softc instead of using a hardcoded table. While there move the call to retrieve the clock frequency into the attach code, and store the value in the softc as well. This will allow a future ACPI attachment driver to supply its value in different fashion. ok kettenis@
2020-11-13Convert array of two-element arrays into a much more readable array ofPatrick Wildt
structs. ok kettenis@
2020-11-13Add define for the status register's Arbitration Lost bit.Patrick Wildt
2020-11-13On VF610 the registers are a single byte apart, so introduce a regshiftPatrick Wildt
variable so that read/write can calculate the correct register offset. ok kettenis@
2020-11-13Even though the registers are 16-bit wide, the upper 8 bits are alwaysPatrick Wildt
reserved. It is fine to use byte-wide access on those registers, which will be necessary to support VF610. Tested on i.MX6 by kettenis@ and on i.MX8MQ by myself ok kettenis@
2020-11-12Reconfigure the COMPHY mode when we find an SFP and configure inband mediaMark Kettenis
status updates in that case. This probably won't work properly on the 10G ports of the MACCHIATOBin "double shot" model, but makes all SFP cages work on the "single shot" model. ok patrick@
2020-11-12FDT-based I2C drivers should not use OF_* API in the match code, sincePatrick Wildt
on machines with ACPI ia->ia_cookie will be an ACPI node instead of an OF node. We'll still get into trouble with APCI devices that provide a string that matches, but we'll worry when that happens. ok kettenis@
2020-11-10Enable optical output when bringing an interface up and disable it againMark Kettenis
when bringing the interface down. Disable optical output when the driver attaches to be sure. ok claudio@, patrick@
2020-11-10Add interfaces to control optical output of an SFP.Mark Kettenis
ok claudio@, patrick@
2020-11-10Fix previous commit; using > 0 to check a pointer isn't quite right.Mark Kettenis
2020-11-10If possible, check the MOD-DEF0 signal to detect the presence of an SFP.Mark Kettenis
ok patrick@
2020-11-09Rework MAC initialization code. Properly turn comphy off and on againPatrick Wildt
on re-initialization. Make sure interrupts are masked while we are doing those bits dirty. This fixes issues with network stopping after the first down/up cycle.
2020-11-09Clear TX sent counter on up/down.Patrick Wildt
2020-11-09On interface down, drop received packets by adding them back into thePatrick Wildt
buffer manager pool.
2020-11-09Small whitespace cleanup.Patrick Wildt
2020-11-08Add supported media types for SFPs.Mark Kettenis
ok patrick@
2020-11-08U-Boot might not have cleaned its pools. The pool needs to be emptyPatrick Wildt
before we fill it, otherwise our packets are written to wherever U-Boot allocated memory. Cleaning it up ourselves is worrying as well, since the BM's pages are probably in our own memory. Best we can do is stop the BM, set new memory and drain the pool. Tests show that this still returns U-Boot's entries. Now, where have those been stored... in HW or in memory?
2020-11-08Hand the pool a physical address, not a virtual one.Patrick Wildt
2020-11-08Check that DMA memory has been allocated for the rings and the BM. WhilePatrick Wildt
there remove a memset that's already been done by the allocator.
2020-11-07Add clock support for i.MX8MP. This variant uses essentially thePatrick Wildt
same layout as the i.MX8MM, which means that all supported clocks so far have the same selection of parents and allows reusing the i.MX8MM code.
2020-11-06The ClearFog GT 8K device tree references the PP22's gate clockPatrick Wildt
instead of the core clock, so add this one to mvclock(4) as well. ok kettenis@
2020-11-03Have mvpp(4) pass MII flags depending on the phy mode specified inPatrick Wildt
the device tee. This allows my ClearFog GT 8K to get the 1G link up. ok kettenis@
2020-11-03Disable HW PHY polling. It's enabled by default.Patrick Wildt
2020-10-12Add support for the i.MX8M AHB clocks. These behave just like all thePatrick Wildt
other composite clocks. With this we can get the frequency for the OCOTP.
2020-10-12OCOTP's parent clock is the IPG clock on i.MX8M.Patrick Wildt
2020-10-08Register sxitwi(4) in the I2C framework.Patrick Wildt
ok kettenis@
2020-09-29Add support for A64 UART resets.Mark Kettenis
ok patrick@
2020-09-13Add support for the RK3308 MAC.Jonathan Matthew
ok kettenis@
2020-09-13Correct the property name used to look up the delays for the phy resetJonathan Matthew
process. ok kettenis@ as part of a larger diff
2020-09-08Add RK3308 temperature sensors.Jonathan Matthew
ok kettenis@
2020-09-08Add RK3328 PWM, also found in the RK3308.Jonathan Matthew
ok kettenis@
2020-09-06Add RK3308 clocksJonathan Matthew
ok kettenis@
2020-09-04Add RK3308 pinctrl supportJonathan Matthew
ok kettenis@
2020-09-04Add RK3308 GRFJonathan Matthew
ok kettenis@
2020-08-30PLL1(CPU_PLL) stability improvement for Allwinner H3/H2+SASANO Takayoshi
Due to unstable of PLL1, sometimes the system has hanged up especially at boot. This is observed at Allwinner H3/H2+ processor. To solve the problem, PLL1 setting procedure is same as Linux. 1. change clock source to 24MHz 2. wait 1usec (new) 3. disable PLL1 (new) 4. set new NKMP value, but M should be 1 5. re-enable PLL1 (new) 6. wait PLL1 stable (modified) 7. change clock source to PLL1 8. wait 1usec (new) Once disable PLL1 before setting NKMP is very important. And, sometimes LOCK flag is set even if PLL has not locked yet so wait for PLL is modified with simple delay() by the value of PLL_STABLE_TIME_REG1 register. Not only Allwinner H3/H2+ but also all (i.e. A64) Allwinner processors datasheet has "If the clock source is changed, at most to wait for 8 present running clock cycles." sentence at CPU clock source selection field of CPU/AXI configuration register. But this is ambiguous that _who_ should do _what_ during that cycles. It is unclear that changing clock source itself invoke PLL1 unstability. For safety, added 1usec wait after changing clock source like Linux. ok by kettenis@, thanks to adr at sdf dot org
2020-08-24Enable UHS-I support. No SDR104 support though since it doesn't seem to workMark Kettenis
reliably.
2020-08-22Rework unicast/multicast configuration. Keep note that this only changesPatrick Wildt
the code configuring the parser, we do not yet add the proper multicast filters.
2020-08-22Correct oversize rxq initialization in the classifier.Patrick Wildt
2020-08-22IPv4 protocol parser init fixup and a few whitespace fixes.Patrick Wildt
2020-08-22Consistently use sizeof(pe) or sizeof(*pe) for the parser entry struct.Patrick Wildt
2020-08-22Use sizeof(variable) instead of using a macro for the length parameter.Patrick Wildt
2020-08-22Simplify some code by getting rid of an extra variable.Patrick Wildt
2020-08-22More consistent use of the BIT() macro.Patrick Wildt
2020-08-22Simplify check for return code.Patrick Wildt
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