Age | Commit message (Collapse) | Author | |
---|---|---|---|
2018-08-30 | fix memory leak in an error path | Jonathan Gray | |
ok patrick@ | |||
2018-08-28 | avoid uninitialised variable use in an error path | Jonathan Gray | |
ok kettenis@ | |||
2018-08-27 | Add hitemp(4), a driver for the temperature sensors on the HiSilicon Hi3660 | Mark Kettenis | |
and Hi3670 SoCs. | |||
2018-08-27 | Add 64-bit DMA support. Enable DMA on HiSilicon SoCs. | Mark Kettenis | |
ok patrick@ | |||
2018-08-27 | Add hiclock(4). Make sure hireset(4) attaches early. | Mark Kettenis | |
2018-08-27 | Add hirest(4), a driver to support reset signal controller blocks on | Mark Kettenis | |
HiSilicon SoCs. | |||
2018-08-27 | Add glue for the USB3 controller on the HiKey 970. | Mark Kettenis | |
2018-08-27 | handle 16 bit register width required for omap3/omap4 | Jonathan Gray | |
ok kettenis@ | |||
2018-08-27 | Add an interface that allows drivers to claim a framebuffer and check | Mark Kettenis | |
whether another driver has already claimed a framebuffer. Use this in radeondrm(4) and simplefb(4) to prevent the latter from attaching if radeondrm(4) is attached to the hardware that provides the framebuffer set up by the firmware. ok mlarkin@ | |||
2018-08-27 | HiSilicon SoCs pre-divide the clock by a factor 8. | Mark Kettenis | |
2018-08-26 | Add pinctrl(4), a generic pin mux driver. | Mark Kettenis | |
ok patrick@ | |||
2018-08-26 | Add plgpio(4), a driver for the ARM PrimeCell GPIO (PL061) peripheral. | Mark Kettenis | |
ok jsg@, patrick@ | |||
2018-08-26 | Add support for HiSilicon Hi3660 (Kirin960) and Hi3670 (Kirin970). | Mark Kettenis | |
2018-08-22 | Initialize bridge registers instead of relying on ppb(4) to do it for us. | Mark Kettenis | |
This gives us more control over the I/O windows that we expose such that we can make enough address space available for graphics cards. | |||
2018-08-21 | Implement address translation. Makes I/O space access work. | Mark Kettenis | |
2018-08-20 | Enable I2C clocks in imxiic(4). | Patrick Wildt | |
2018-08-20 | Add the i.MX8MQ eCSPI clocks. | Patrick Wildt | |
2018-08-17 | The official name for the ssdfb(4) reset GPIO attribute uses plural form. | Patrick Wildt | |
2018-08-17 | Support reading and using serveral device tree attributes for ssdfb(4), | Patrick Wildt | |
since some OLED display controller settings can change depending on the actual hardware integration. | |||
2018-08-13 | Support CPU frequency scaling on NXP i.MX8M. | Patrick Wildt | |
ok kettenis@ | |||
2018-08-09 | Hook up the rasops text emulation functions so we only write out | Patrick Wildt | |
the characters that changed, and only when they change. This replaces writing out the whole framebuffer every 100ms with a partial update mechanism. Now the system stays responsive and does not slow down anymore due to the periodic update. | |||
2018-08-09 | Make imxesdhc(4) pass per-function cookies to the SD/MMC bus. | Patrick Wildt | |
ok kettenis@ | |||
2018-08-08 | Implement IRQ masking and unmasking in imxgpio(4). | Patrick Wildt | |
2018-08-06 | Give the FDT interrupt API a more generic naming by replacing the | Patrick Wildt | |
arm_intr_* prefix with fdt_intr_*. ok kettenis@ | |||
2018-08-04 | Implement a few missing RK3288 clocks and implement resets. | Mark Kettenis | |
2018-08-03 | Pass PCIe requester ID as sideband data here as well. | Mark Kettenis | |
2018-08-03 | Implement setting the CPU clock for Allwinner H3/H5 SoCs. | Mark Kettenis | |
2018-08-03 | Also attach as a regulator if the FDT provides the fixed voltage value. | Mark Kettenis | |
Restore fixed voltage at reboot time to prevent hangs after a warm reset if DVFS is active. | |||
2018-08-03 | Implement DVFS support. | Mark Kettenis | |
ok patrick@ | |||
2018-08-02 | Add I2C attachment code to ssdfb(4). The difference between the I2C | Patrick Wildt | |
and SPI bus is simply how to let the chip know it's a command or data transfer. Otherwise we push the very same bits. | |||
2018-08-01 | Fix various RK3399 clocks and add support for getting the clock frequency | Mark Kettenis | |
of the clocks that we can set. Assign clock rates (and parents) based on the "assigned-clocks" device tree property, but only on RK3399 for now as the code for the other Rockchip SoCs isn't quite ready yet. Last but not least, fixup a mistake on the firmware for the Theobroma Systems RK3399-Q7 module such that the "big" cluster uses BPLL as intended. | |||
2018-08-01 | Implement a partial update mechanism. Since the SPI-connected display | Patrick Wildt | |
cannot read the framebuffer memory, we have to push the framebuffer to the display. ssdfb(4) will now be able to update only a certain region region of the framebuffer as soon as there is infrastructure to trigger it. | |||
2018-07-31 | Display color depth alongside resolution when attaching simplefb(4). | Frederic Cambus | |
OK kettenis@, deraadt@ | |||
2018-07-31 | Stop reversing bytes read from the framebuffer. That was added since | Patrick Wildt | |
the 8x16 font showed horizontally flipped characters, but as it turns out the issue is that with 8-bit wide fonts we use optimized rasops code that apparently writes out the character with reversed bitorder. | |||
2018-07-31 | Implement setting the voltage of the regulators. | Mark Kettenis | |
2018-07-31 | Correctly set the dividers for the clock of the "big" cores. | Mark Kettenis | |
2018-07-31 | Fix setting the voltage; the code was using the wrong variable as a step size. | Mark Kettenis | |
Includes some cosmetic fixes as well. | |||
2018-07-30 | Add support for the GIC v3 ITS and use it to implement MSI support for | Mark Kettenis | |
rkpcie(4). ok patrick@ | |||
2018-07-30 | Add ssdfb(4), a driver for the SSD1309 controller that drives an | Patrick Wildt | |
128x64 OLED display. With the typical 8x16 font we get 4 rows with 16 characters each on it. The controller can be driven using I2C, 3-wire and 4-wire SPI. This commit includes support for the 4-wire protocol. ok deraadt@ | |||
2018-07-28 | Make use of PCI_FLAGS_MSI_ENABLED such that drivers for hardware with broken | Mark Kettenis | |
MSI support can selectively disable the use of MSI. | |||
2018-07-26 | Add imxspi(4), a driver for the i.MX SPI controller. This is the first | Patrick Wildt | |
SPI controller in our tree. Add a basic generic SPI infrastructure as well. ok kettenis@ | |||
2018-07-26 | Implement calculating the SPI controller frequency in imxccm(4). | Patrick Wildt | |
ok kettenis@ | |||
2018-07-24 | Add support for the i2c controller on the Marvell ARMADA 7K/8K SoC as well. | Mark Kettenis | |
ok patrick@ | |||
2018-07-24 | Add clock needed to support the i2c controllers on the Marvell ARMADA 7K/8K. | Mark Kettenis | |
ok patrick@ | |||
2018-07-24 | The I2C controller on the Allwinner hardware is actually a modified | Patrick Wildt | |
Marvell controller. The difference is essentially register offsets and a clock divider calculation based on a power of two. Also this particular hardware needs a delay after sending a stop and before reading the status register since apparently the data doesn't propagate fast enough. This makes sxitwi(4) work on the Marvell Armada 38x. ok kettenis@ | |||
2018-07-23 | The imxiomuxc(4) node itself can also contain a set of pins to | Patrick Wildt | |
configure. These are pins that should be configured to a sane state and are not necessarily referenced by another node. ok kettenis@ | |||
2018-07-20 | match on marvell,armada-38x-uart linux >= 4.18-rc1 changed the compat | Jonathan Gray | |
string from snps,dw-apb-uart in b7639b0b15ddd1a4686b0142e70dfb122eefc88f ok patrick@ | |||
2018-07-09 | Basic support for SFP modules in mvneta(4). SFP modules are basically | Patrick Wildt | |
hotpluggable PHYs whose status can either be read using an I2C-connected PHY, or using in-band status management implemented in the controller itself over SGMII. With this, 802.3z SFPs work on mvneta(4). | |||
2018-07-02 | Allow pluart(4) to attach to acpi(4). | Mark Kettenis | |
ok mlarkin@, patrick@ | |||
2018-07-01 | Use generated string for the bus number extent. | Mark Kettenis | |