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path: root/sys/dev/ic/nvme.c
AgeCommit message (Collapse)Author
2017-08-18Avoid a NULL dereference in an error path. Coverity CID 1453201.Jonathan Gray
ok mikeb@
2017-06-12typo; from bryan vyhmeisterTheo de Raadt
2017-05-29Add hibernate support for nvme(4). This creates a separate IO queue that isJonathan Matthew
only active during hibernation, preallocating the the submission and completion queues during attach as they need to be page-aligned. tested on an x270 that successfully hibernates now. ok dlg@
2017-05-27nvme: Don't set prp1 for DEL_IOCQStefan Fritsch
NVM_ADMIN_DEL_IOCQ does not need prp1 (just as NVM_ADMIN_DEL_IOSQ). Remove what is likely a cut'n'paste error from the *_ADD_* code. tested by claudio@ ok jmatthew@
2017-05-27nvme: Add suspend/resume codeStefan Fritsch
Based on an initial patch by ehrhardt@ . Thanks to claudio@ for testing and deraadt@ for advice. "go ahead" deraadt@
2017-05-12subtract one sector from the disk size before passing it back to theJoshua Stein
scsi layer, which will add one sector back fixes incorrect disk size reporting which was causing fdisk to create a protective MBR of one too many sectors, which caused our EFI bootloader to fail to recognize it as a GPT disk ok dlg
2017-04-08A pile of sizes to free(9). In test for a few days in snapshots.Theo de Raadt
Errors will result in nice clean panic messages so we know what's wrong. Reviewed by dhill visa natano jsg.
2016-11-15Do not use bus_space_{read,write}_8() even on LP64 archs,Martin Pieuchot
some (broken) controllers require ordered split transfers. From linux a310acd7a7ea53533886c11bb7edd11ffd61a036 Tested by gonzalo@, ok dlg@
2016-11-15Mask non relevant bits when pritting version number.Martin Pieuchot
Makes gonzalo@'s Macbookair7,1 NVMe report the correct version. ok dlg@
2016-10-25mask and unmask the interrupt source in an intx specific intr handler.David Gwynne
it seems devices using levelled intx interrupts need to explicitely ack interrupts by masking and unmasking the source around the completion ring handling. without this completions can be lost, which in turn causes long (permanent?) stalls in the block layer under heavy write load. ive experienced this problem with an intel nvme part that only has intx and msix support. because we dont support msix yet we only use intx on it. it appeared to lock up before this fix. this has been tested on both that intel board and a samsung with msi. this fix was based on work found in code by nonaka
2016-05-20check we allocated the cq, not the sq, after trying to allocate the cqDavid Gwynne
found by NONAKA Kimihiro while he was porting nvme to netbsd.
2016-04-18allocate an array of entries, not pointers for the queuesDavid Gwynne
this solves my memory corruption problem with a samsung sm951 in a particular slot on a dell 2950. hilariously, i had picked values which masked this problem on sparc64. i randomly picked 128 as the number of entries on the queues, and dmamem allocs get rounded up to PAGE_SIZE. on amd64 and sparc64 this meant i was asking for 128 * 8 (sizeof pointer), or 1024 bytes, which got rounded up to 4096 and 8192 on each arch respectively. 128 * 64 (the size of a submission queue entry) is 8192, so it worked fine on sparc64 for that reason, but randomly blows up on amd64. the 2950 above allocated mbufs out of the page after the submission queue, which i ended over overwriting. anyway. let's move on.
2016-04-14shorten the io path slightlyDavid Gwynne
2016-04-14apparently it's spelled NVMe, not NVMEDavid Gwynne
2016-04-14provide a shutdown hook that follows the procedure in the docsDavid Gwynne
2016-04-14implement translation of scsi SYNC CACHE to nvme FLUSHDavid Gwynne
2016-04-14bump openings to 64 to match the number of ccbs.David Gwynne
still a bit magical, but good enough for now.
2016-04-14if io needs more than two prpe slots, overflow into the ccb prplDavid Gwynne
this should be enough to make io reliable
2016-04-14reallocate the ccbs after we figure out how big the sgls can beDavid Gwynne
we run with 2 entries for the nvme controller identify, and then bump it up to cover the maxphys divided by the page size we negotiate.
2016-04-14set the scsi status to SCSI_OKDavid Gwynne
2016-04-14allocate dma memory for ccbs to use as prpe listsDavid Gwynne
prpe is short for Physical Region Page Entry. this is where long lists of dma regions go when they wont fit into a submission queue entry.
2016-04-14dont attach if the min nvme page size is bigger than the cpu page sizeDavid Gwynne
nvme and the host cpu need to agree on the page size because its the implicit size of the elements in the chips scatter gather lists. if the min nvme size is greater than the cpus page size then we cant guarantee that io buffers are contig for nvme pages. nvme 1.1 provides an alternative sgl mechanism, so if this really becomes a problem in the future we can fix it on 1.1 and later devices.
2016-04-14dont complete scsi writes twiceDavid Gwynne
it ends up being a use after free, which disagrees with the midlayer.
2016-04-14WAITOK for the dmamap create for ccbs tooDavid Gwynne
again, only called during autoconf which is a kind of process context.
2016-04-14cut the memory for io buffers up into page sized chunksDavid Gwynne
nvme 1.0 does not use conventional scatter gather lists of address+length pairs. instead, it simply expects a list of page addresses. this should be ok if we only feed it single VA chunks which map directly to only whole physical pages. nvme 1.1 introduced another scather format, but still accepts the 1.0 format too. we'll stick to the 1.0 format so we can support 1.0 devs.
2016-04-14check both the admin and io queue for completions in the interrupt handlerDavid Gwynne
this means we'll notice io completions.
2016-04-14dont put names in arguments.David Gwynne
2016-04-13implement handling of scsi reads and writesDavid Gwynne
ive only tested reads, and not very big ones. nvme 1.0 has a very stupid/naive idea about what constitutes a scatter gather list. it assumes io is in whole pages in memory, but i dont know if that is true in our kernel. this could be cleaned up a bit, and it currently runs with a single opening for the whole scsi layer and a bunch of magic values for the size and number of the io queues.
2016-04-13enable interrupts before attaching the scsibusDavid Gwynne
2016-04-13allocate a queue for io commands and tell the chip about it.David Gwynne
this is necessary to run reads and writes against the device.
2016-04-13nvme_q_create() issues the commands to tell the chip about io queuesDavid Gwynne
2016-04-13stub out handling of TEST_UNIT_READY, PREVENT_ALLOW, and START_STOPDavid Gwynne
at the moment this just pretends the commands completed fine.
2016-04-13implement handling of scsi read capacity commandsDavid Gwynne
read cap 16 claims the devices are thin.
2016-04-13implement basic scsi inquiry handlingDavid Gwynne
most values are as per the nvm to scsi mapping guide. this doesnt do vpd at all, so no devids or serial numbers just yet.
2016-04-13implement the guts of the scsi probe and free functionDavid Gwynne
probe issues a namespace identify against the "target". if it works it stashes a copy of the info, otherwise it tells the midlayer to avoid it. free gets rid of the stashed info.
2016-04-13wire up the scsi midlayer. scsibus should appear after this.David Gwynne
2016-04-13allocate an array of things to hold info about namespacesDavid Gwynne
so far the only useful info is namespace identify info
2016-04-13stash the controller identify and number of namespaces in the softc.David Gwynne
the nn is used to size the scsi bus, and the controller identify is used to build responses for various scsi commands.
2016-04-13provide an scsi_adapter and stub functions for emulation to sit inDavid Gwynne
2016-04-13nvme_sqe_fill will post a copy of an sqe from a callerDavid Gwynne
2016-04-13poll for command completion on the cqe itll be of calling nvme_intrDavid Gwynne
2016-04-13make nvme_poll return the flags from the completion queue entryDavid Gwynne
it's still 0 on success, but is the actual bits rather than a mashup of it
2016-04-13keep track of the queue id in nvme_queue.David Gwynne
2016-04-13rename idx to id in nvme_q_allocDavid Gwynne
make it a u_int16_t like the hw while here.
2016-04-13nvme_dmamem_alloc runs in autoconf or process context, so it can sleepDavid Gwynne
2016-04-12shuffle attach so we read chip capabilities before operating on itDavid Gwynne
most importantly this gets the proper timeout for chip enables/disables.
2016-01-15when enabling the controller, wait till CSTS.RDY lights up.David Gwynne
2016-01-15feng shui.David Gwynne
dont need a billion tabs for the function prototypes. just some akward line wrappings.
2016-01-15handle the version register like ahci.David Gwynne
2016-01-15wrap up dma syncs for the whole mapping.David Gwynne
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