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path: root/sys/dev/ic/silireg.h
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2007-04-07Add some more device status related register definitions.Christopher Pascoe
2007-04-07Correct offset for global interrupt status register.Christopher Pascoe
2007-04-07this diff covers two changes, but theyre very tightly tied together.David Gwynne
implement long sgls by allocating 512 bytes per command, which gives us 7 scatter gather tables to fill in per command. we can now do proper sized io. commands are still polled though, so its very very slow ;) since you cant submit more than 128 bytes using direct command submission, we needed to implement indirect submission too. this almost worked, but i gave the controller to pascoe before i got it working. he did the fixes to my dumb dumb mistakes. thanks pascoe. thascoe.
2007-04-05finish resetting the device by sending a soft reset via the post_directDavid Gwynne
mechanism, and then read the device signature.
2007-04-05control bits in the prb. shuffle things around a bit...David Gwynne
2007-04-05start defining the scatter/gather bits and the port request blocks (PRBs).David Gwynne
2007-04-04interrupt enable set/clear defnsDavid Gwynne
2007-04-04port control clear bitsDavid Gwynne
2007-04-01Correct some sili port offsets.Jonathan Gray
ok dlg@
2007-03-31more bits and the %b thing for port set/statusDavid Gwynne
2007-03-31Port Control Set register defsDavid Gwynne
2007-03-31initial atascsi glue.David Gwynne
2007-03-30define the size and offsets for each ports set of registersDavid Gwynne
2007-03-26bits for the global control registerDavid Gwynne
2007-03-26oops, 64bit memory bars.David Gwynne
2007-03-24port registersDavid Gwynne
2007-03-24global register definitionsDavid Gwynne
2007-03-22read and write funcs for the global register spaceDavid Gwynne
2007-03-22map the global and port register spaces.David Gwynne
2007-03-22import sili(4) so it can be worked on in the tree. this will support theDavid Gwynne
silicon image 3124/3132/3531 sata chipsets eventually. so far this is the autoconf glue, an actual match routine for the 3124, and interrupt establishment code. it is split up between pci and ic cos there are cardbus variants of these controllers that we can support in the future. thanks to jolan@ for the name, it was better liked than my initial suggestion of siisl(4).