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found by deraadt@
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prevents dmesg spam when we return this ccb to the free list.
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with it. prevents free panics on sparc64.
found by deraadt on a v215.
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and its not helping us on those that arent.
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overall interrupt rate.
#define AHCI_COALESCE to enable.
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to avoid tripping a KASSERT in the case when there is more than one
outstanding command.
ok dlg@
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active commands when an error is encountered.
ok dlg@
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ok dlg@
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do ncq, so this diff quirks it.
tested by jasper@
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quirk a few things before it will work.
this blacklists that controller in ahci so pciide will be able to match it
instead.
found by jasper@
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that we don't accidentally complete any other outstanding commands.
This introduces wrappers around get_ccb and put_ccb that can temporarily
stash our outstanding command state while we are issuing recovery commands.
This is just the first step in NCQ recovery - for now we will reset the port
on error which will permit further commands to be issued after a NCQ error.
ok dlg@
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successfully and not the ones that had actually failed to complete when unable
to recover from an NCQ error.
ok dlg@
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list of pci devices.
WARNING: this will cause your disks to change name (wd -> sd) on a
supported controller.
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out or erroring around the cache flush time.
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are seeing a panic at halt time.
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This includes a nasty hack to reduce openings and throw away command slots
if the device supports a lower queue depth than the host controller does.
Yes, we're thinking about a better solution.
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generation of interrupts when they arrive.
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Because you cannot have NCQ commands active at the same time as standard
(non-queued) commands, we must introduce a queueing scheme into the driver.
This scheme ensures that a standard command is only issued to the drive when
all currently active NCQ commands have finished, and that NCQ command issue
is delayed when we have a pending standard command.
Additionally, the queueing scheme adds a constraint to ensure that there are
never more than two standard commands issued on a port at once. This should
ensure that commands become active in the order they were submitted (regardless
of their command slot number) both initially and when the port is reactivated
after error recovery.
These points mean that issuing a standard command effectively serialises the
port, which may help us implement meaningful I/O barriers in the future.
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seeing things attach to the scsibus.
ok pascoe@
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it a bit easier to read. there are variations on this, but they can be
defined later.
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reset with during error recovery. Also, ensure that that CCB has been
stopped on the chip before putting it back in the pool.
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error handling.
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always return ATA_COMPLETE in the polled transfer case. Also, respect the
passed in timeout value when polling.
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these since last year, but i didnt see the point till the code would be
useful anywhere.
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etc, just work.
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so that atascsi can deal with it.
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before we enable AHCI, so enable it before resetting saved capabilities.
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etc), and request that the D2H FIS at the completion of all (DMA) commands
generate an interrupt.
This makes each data transfer generate one interrupt instead of two and
should guarantee that the interrupt that is generated actually arrives
after the command has completed.
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works.
From dlg@
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simply include a pointer to the command FIS that we will issue to the device.
Include another space where we can copy back an error register set from a
failed command.
This means that we can now build and issue arbitrary commands from atascsi,
and retrieve errors back.
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atascsi will be driving, and add it to the AHCI CCB.
This effectively gives us all the resources we need for a transfer in one
hit, meaning that we don't need to worry about whether we will have a pool
shortage or not enough CCBs. The SCSI mid layer should take care to never
exceed the number of CCBs we have available, based on our sc_link.openings.
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and shut down the controller upon error (no recovery).
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a mask.
Fix some typos and try to keep functions in the same order as prototypes
to make the code easier to navigate.
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- add a ccb_done member to the ahci_ccb, which points to a function that
is used to complete the current xfer
- ccbs no longer rely on an ata_xfer being provided for submission to work
- ahci is stupid and has no way to telling you the difference between an
empty command slot, and a completed command. we keep track of active
commands with ap_active in ahci_port, so we dont try and complete commands
we havent actually submitted
- ahci_start simple submits a command to the hardware now
- provide the start of an interrupt handler for each port (which is not yet
called by the controllers interrupt handler)
- provide an ahci_poll which is built on top of ahci_start and
ahci_port_intr
- remove the fake ata_xfers from the softreset path
- on completion of an ahci command, sync the relevant dma memory
- provide a completion path for ata_xfers which syncs the xfers buffer
and calls the xfers completion handler
in atascsi.c:
- start defining the contents of the response to an ATA IDENTIFY command
specific to SATA
- implement the faking of scsi inquiries, so now you'll actually see a disk
attach to ahci.
- start implementing a fake scsi read capacity. it presents a fake geometry
though, so dont get too excited when ahci magically makes your disk have a
terabyte in size.
lots of discussion, help, tweaks, and an ok from pascoe@
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dont have to carry the cmd_tables dva around in the ccb anymore.
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ever zero out the whole command header.
Also add some diagnostic checks to ensure we don't violate any of the
controller's DMA address/size restrictions.
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addresses for me when it writes to the registers. Don't swap them manually.
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explicit by including pointers to both of them in the ccb.
Inspired by dlg@
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