| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2007-07-22 | clear the IFF_ALLMULTI flag when the interface goes down. | David Gwynne | |
| 2007-07-22 | the softc variable is sc, not sp. | David Gwynne | |
| 2007-05-28 | use memcpy when copying to/from the fifos, apparently gcc can do a better | David Gwynne | |
| job of optimising it. | |||
| 2007-05-26 | chop ETHER_ALIGN off the size of the packet we tell the hw we can do | David Gwynne | |
| 2007-05-26 | ETHER_ALIGN rx mbuf so that it works on strict alignment archs. OK dlg@ | Claudio Jeker | |
| 2007-05-26 | correctly byteswap the mac address when moving it on and off teh card | David Gwynne | |
| 2007-05-17 | copy the lladdr from the arpcom struct onto the hardware when the interface | David Gwynne | |
| is brought up. this driver now supports all the features our network layer expects of it. | |||
| 2007-05-17 | support changing the mtu up to the maximum frame size it currently | David Gwynne | |
| supports (MCLBYTES). | |||
| 2007-05-16 | add support for multicast addresses. this adds the add/del multi handlers | David Gwynne | |
| to the ioctl, and programs the multicast filter in tht_iff. we are not using the perfect multicast filters, only the imperfect one. i think there is a requirement that addresses in the perfect filter be in order, but im not sure how to do that nicely (yet). this has taken a long time because i dont know how to write c. | |||
| 2007-05-08 | make a start at dealing with interface flags. this toggles the hardware | David Gwynne | |
| promiscuity depending on the if_flags IFF_PROMISC bit. | |||
| 2007-05-08 | add the multicast filter registers | David Gwynne | |
| 2007-05-08 | write the mac back to the chip when we bring it up. | David Gwynne | |
| 2007-05-06 | point the macros for the interrupt coalescing registers at the right | David Gwynne | |
| location. they moved from what the doco says to somewhere else. pointed out by Nadav Shemer (thanks) | |||
| 2007-05-06 | typo | David Gwynne | |
| 2007-05-04 | the hardware does checksumming on rx as well. mark the mbufs with what the | David Gwynne | |
| hw says. | |||
| 2007-05-04 | advertise tx checksumming to the network stack, and tell the hardware to | David Gwynne | |
| do it. | |||
| 2007-05-04 | increase the number of tx and rx descriptors from 64 to 128 each | David Gwynne | |
| 2007-05-04 | call the right function to fill the rxf fifo after rxd | David Gwynne | |
| 2007-05-04 | disable debugging output | David Gwynne | |
| 2007-05-04 | put more rx descriptors back on the chip straight after we've taken some | David Gwynne | |
| off. | |||
| 2007-05-04 | wrap the wptr round when we hit the end of the fifo. | David Gwynne | |
| 2007-04-30 | fix dmesg; ok dlg | Theo de Raadt | |
| 2007-04-29 | missing arguments in a couple of printfs. | David Gwynne | |
| patch from Tim van der Molen | |||
| 2007-04-29 | Nadav Shemer of Tehuti Networks is magical. | David Gwynne | |
| not leaving the gap in the txt fifo when uploading the firmware was the cause of my fifo write bug in tht_start. because i was filling the whole fifo, i was writing the wptr back to its original position. because of this i dont think the firmware thought i had written anything. only the last short chunk would have been noticed, which strikes me as possibly confusing to the chip. this diff removes the delay at the top of tht_fifo_post. one less XXX :) | |||
| 2007-04-29 | clocks and pll register bits | David Gwynne | |
| 2007-04-29 | we dont want to completely fill fifos, so leave a gap when we calculate | David Gwynne | |
| how much of the fifo we want to write firmware to. from Nadav Shemer at Tehuti Networks | |||
| 2007-04-29 | when we post a fifo we're giving the dma mem back to the hardware, so we | David Gwynne | |
| need a presync, not a postsync. another good find by Nadav Shemer at Tehuti Networks | |||
| 2007-04-29 | when completing a tx pkt, put it back on the tx free list, not the rx one. | David Gwynne | |
| found by Nadav Shemer at Tehuti Networks. | |||
| 2007-04-27 | Correct typo in comment, no code changes | Chad Loder | |
| 2007-04-27 | Fix copy/paste-o in offset of TDINTCM register jointly spotted by dlg and | Chad Loder | |
| myself. This register controls TX interrupt and packet coalescing. OK dlg@ | |||
| 2007-04-27 | my txt fifo write bug is extremely strange. i need a delay before the | David Gwynne | |
| wptr write for it to work. delay(75) works, delay(67) doesnt, so im disabling the fifo debug and adding delay(100) till this is worked out properly with tehuti. | |||
| 2007-04-25 | hook the rx path up. | David Gwynne | |
| despite having written it without being able to test, there was only one real bug. i wasnt keeping track of the mbuf in the rx init path, so when the completion tried to use it, it was dereferencing random memory. | |||
| 2007-04-25 | add some dprintfs to the fifo handlers. | David Gwynne | |
| enabling these makes tx completions occur. i wish i could figure out why. | |||
| 2007-04-25 | when populating the rxf fifo, actually sync the rxf fifo at the start and | David Gwynne | |
| end of it, not txf. still doesnt fix my bug | |||
| 2007-04-25 | we only have to mask interrupts once when we bring the interface down | David Gwynne | |
| 2007-04-25 | i got a reg init wrong, still no tx completion though. | David Gwynne | |
| 2007-04-25 | enable tx completion interrupts and provide handling for them. | David Gwynne | |
| unfortunately theres a bug somehwere. i had this working 6 hours ago, but after scrubbing that diff it no longer completes packets. so annoying. | |||
| 2007-04-25 | fix a dprintf in the debug path | David Gwynne | |
| 2007-04-25 | more register init in tht_up | David Gwynne | |
| 2007-04-25 | put a two second timeout on the chip init after the firmware is loaded | David Gwynne | |
| 2007-04-25 | shift some bits like the spec says i should. | David Gwynne | |
| 2007-04-25 | format string fix | David Gwynne | |
| 2007-04-25 | add some debug to the tx paths so i can see packets go on and off the hw. | David Gwynne | |
| 2007-04-25 | fix the conditions that the tx free path keeps looping on so that it will | David Gwynne | |
| process all available descriptors, instead of leaving one behind. | |||
| 2007-04-25 | configure the 10G mac and enable (more) interrupts when the interface is | David Gwynne | |
| brought up. mask them again when the interface goes down. | |||
| 2007-04-25 | split tht_fifo_ready into tht_fifo_writable and tht_fifo_readable. the way | David Gwynne | |
| you determine usable space in the fifo is different between read and write fifos, not half different like i thought it was. | |||
| 2007-04-25 | start implementing interrupt handling. | David Gwynne | |
| the firmware generates an interrupt when it detects a link state change, so we dont have to poll for it like other nics do. this sets it up so the interrupt is handled even if the nic is down at the time. you can plug and unplug the cable now and see pretty dmesg output. | |||
| 2007-04-25 | add more register definitions, in particular the interrupt ones. | David Gwynne | |
| 2007-04-25 | im an idiot. for (;;) { } while (condition); loops forever, no matter what | David Gwynne | |
| the condition is. | |||
| 2007-04-25 | add some debug goo to be used soon | David Gwynne | |
 |
index : src | |
| OpenBSD base system |
| summaryrefslogtreecommitdiff |