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path: root/sys/dev/pci/if_tht.c
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2008-11-28Eliminate the redundant bits of code for MTU and multicast handlingBrad Smith
from the individual drivers now that ether_ioctl() handles this. Shrinks the i386 kernels by.. RAMDISK - 2176 bytes RAMDISKB - 1504 bytes RAMDISKC - 736 bytes Tested by naddy@/okan@/sthen@/brad@/todd@/jmc@ and lots of users. Build tested on almost all archs by todd@/brad@ ok naddy@
2008-11-23sizeofa -> nitemsDavid Gwynne
2008-10-02First step towards cleaning up the Ethernet driver ioctl handling.Brad Smith
Move calling ether_ioctl() from the top of the ioctl function, which at the moment does absolutely nothing, to the default switch case. Thus allowing drivers to define their own ioctl handlers and then falling back on ether_ioctl(). The only functional change this results in at the moment is having all Ethernet drivers returning the proper errno of ENOTTY instead of EINVAL/ENXIO when encountering unknown ioctl's. Shrinks the i386 kernels by.. RAMDISK - 1024 bytes RAMDISKB - 1120 bytes RAMDISKC - 832 bytes Tested by martin@/jsing@/todd@/brad@ Build tested on almost all archs by todd@/brad@ ok jsing@
2008-09-10Convert timeout_add() calls using multiples of hz to timeout_add_sec()Bret Lambert
Really just the low-hanging fruit of (hopefully) forthcoming timeout conversions. ok art@, krw@
2008-05-13Also report the duplex state of the connection when callingBrad Smith
if_link_state_change() which is always full duplex for tht(4). ok dlg@
2008-05-12Make this compile again.Mark Kettenis
2008-05-12Pass correct argument to timeout_set so that the timeout can break theCan Erkin Acar
loop as intended. ok dlg@
2008-04-11introduce THT_{RXF/TXT}_PKT_NUM macros and use them instead of theThordur I. Bjornsson
hard coded value of 128 for the pkt allocations. OK dlg@
2008-04-04tht is cool cos it generates interrupts when the link state change.David Gwynne
however, tht is uncool cos it generates these interrupts spuriously (up to 8000 times a second). this rate limits the reading of the link state off the hardware to 100 times a second. less bus_space reads is a good thing. tested by and ok thib@
2008-02-02Correct the baudrate handling.Brad Smith
ok dlg@
2008-01-17Set if_baudrate with IF_Gbps(10);Thordur I. Bjornsson
ok dlg@
2008-01-14Zap two usless printfs.Thordur I. Bjornsson
ok dlg@
2007-09-19M_ZERO. all the cool kids are doing it.David Gwynne
2007-07-22clear the IFF_ALLMULTI flag when the interface goes down.David Gwynne
2007-07-22the softc variable is sc, not sp.David Gwynne
2007-05-28use memcpy when copying to/from the fifos, apparently gcc can do a betterDavid Gwynne
job of optimising it.
2007-05-26chop ETHER_ALIGN off the size of the packet we tell the hw we can doDavid Gwynne
2007-05-26ETHER_ALIGN rx mbuf so that it works on strict alignment archs. OK dlg@Claudio Jeker
2007-05-26correctly byteswap the mac address when moving it on and off teh cardDavid Gwynne
2007-05-17copy the lladdr from the arpcom struct onto the hardware when the interfaceDavid Gwynne
is brought up. this driver now supports all the features our network layer expects of it.
2007-05-17support changing the mtu up to the maximum frame size it currentlyDavid Gwynne
supports (MCLBYTES).
2007-05-16add support for multicast addresses. this adds the add/del multi handlersDavid Gwynne
to the ioctl, and programs the multicast filter in tht_iff. we are not using the perfect multicast filters, only the imperfect one. i think there is a requirement that addresses in the perfect filter be in order, but im not sure how to do that nicely (yet). this has taken a long time because i dont know how to write c.
2007-05-08make a start at dealing with interface flags. this toggles the hardwareDavid Gwynne
promiscuity depending on the if_flags IFF_PROMISC bit.
2007-05-08add the multicast filter registersDavid Gwynne
2007-05-08write the mac back to the chip when we bring it up.David Gwynne
2007-05-06point the macros for the interrupt coalescing registers at the rightDavid Gwynne
location. they moved from what the doco says to somewhere else. pointed out by Nadav Shemer (thanks)
2007-05-06typoDavid Gwynne
2007-05-04the hardware does checksumming on rx as well. mark the mbufs with what theDavid Gwynne
hw says.
2007-05-04advertise tx checksumming to the network stack, and tell the hardware toDavid Gwynne
do it.
2007-05-04increase the number of tx and rx descriptors from 64 to 128 eachDavid Gwynne
2007-05-04call the right function to fill the rxf fifo after rxdDavid Gwynne
2007-05-04disable debugging outputDavid Gwynne
2007-05-04put more rx descriptors back on the chip straight after we've taken someDavid Gwynne
off.
2007-05-04wrap the wptr round when we hit the end of the fifo.David Gwynne
2007-04-30fix dmesg; ok dlgTheo de Raadt
2007-04-29missing arguments in a couple of printfs.David Gwynne
patch from Tim van der Molen
2007-04-29Nadav Shemer of Tehuti Networks is magical.David Gwynne
not leaving the gap in the txt fifo when uploading the firmware was the cause of my fifo write bug in tht_start. because i was filling the whole fifo, i was writing the wptr back to its original position. because of this i dont think the firmware thought i had written anything. only the last short chunk would have been noticed, which strikes me as possibly confusing to the chip. this diff removes the delay at the top of tht_fifo_post. one less XXX :)
2007-04-29clocks and pll register bitsDavid Gwynne
2007-04-29we dont want to completely fill fifos, so leave a gap when we calculateDavid Gwynne
how much of the fifo we want to write firmware to. from Nadav Shemer at Tehuti Networks
2007-04-29when we post a fifo we're giving the dma mem back to the hardware, so weDavid Gwynne
need a presync, not a postsync. another good find by Nadav Shemer at Tehuti Networks
2007-04-29when completing a tx pkt, put it back on the tx free list, not the rx one.David Gwynne
found by Nadav Shemer at Tehuti Networks.
2007-04-27Correct typo in comment, no code changesChad Loder
2007-04-27Fix copy/paste-o in offset of TDINTCM register jointly spotted by dlg andChad Loder
myself. This register controls TX interrupt and packet coalescing. OK dlg@
2007-04-27my txt fifo write bug is extremely strange. i need a delay before theDavid Gwynne
wptr write for it to work. delay(75) works, delay(67) doesnt, so im disabling the fifo debug and adding delay(100) till this is worked out properly with tehuti.
2007-04-25hook the rx path up.David Gwynne
despite having written it without being able to test, there was only one real bug. i wasnt keeping track of the mbuf in the rx init path, so when the completion tried to use it, it was dereferencing random memory.
2007-04-25add some dprintfs to the fifo handlers.David Gwynne
enabling these makes tx completions occur. i wish i could figure out why.
2007-04-25when populating the rxf fifo, actually sync the rxf fifo at the start andDavid Gwynne
end of it, not txf. still doesnt fix my bug
2007-04-25we only have to mask interrupts once when we bring the interface downDavid Gwynne
2007-04-25i got a reg init wrong, still no tx completion though.David Gwynne
2007-04-25enable tx completion interrupts and provide handling for them.David Gwynne
unfortunately theres a bug somehwere. i had this working 6 hours ago, but after scrubbing that diff it no longer completes packets. so annoying.
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