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the one changed.
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while (condition) {
do_stuff()
increment_condition /* this was missing */
}
To a for loop like it always should have been. I have no idea what I was
smoking when I wrote this function.
Fixes the crash on hardware that does bit 17 swizzling (turns out the
three I know of are all 945s) as soon as we first unbind an object.
Thank you very much to Brandon Mercer for actually managing to get me a
crash dump so i could debug this, and also for testing the fix.
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libdrm bug recently.
Correct to what was intended.
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accessed by the gpu or needing a flush). Since this implies that the object is
wanted, emit the flush then to save time.
Makes things a lot smoother than before in some GL applications, since
before we were claiming that object needing a flush were unbusy so the
next map stalled the gpu waiting on a flush.
From daniel vetter on intel-gfx.
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conflicts.
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If we just read access to some data that has been accessed by the gpu,
only sleep until the end of the gpus last write (which we track). So
instead of stalling the gpu until the last time accessed, both can read
at the same time (which is allowed and coherent as long as the right
invalidation happens).
Since we check offsets from userland before we exec a batchbuffer, this
helps 965 (with lots of read only relocations in the render path) quite
a lot.
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Before, as well as being kinda nasty there was a very definite race, if
the last reference to an object was removed by uvm (a map going away),
then the free path happened unlocked, this could cause all kinds of
havoc.
In order to deal with this, move to fine-grained locking. Since uvm
object locks are spinlocks, and we need to sleep in operations that will
wait on the gpu, provide a DRM_BUSY flag that is set on a locked object
that then allows us to unlock and sleep (this is similar to several
things done in uvm on pages and some object types).
The rwlock stays around to ensure that execbuffer can have acces to the
whole gtt, so ioctls that bind to the gtt need a read lock, and
execuffer gets a write lock. otherwise most ioctls just need to busy the
object that they operate on. Lists also have their own locks.
Some cleanup could be done to make this a little prettier, but it is
much more correct than previously.
Tested very very vigorously on 855 (x40) and 965 (x61s), this found numerous
bugs. Also, the I can no longer crash the kernel at will.
A bunch of asserts hidden under DRMLOCKDEBUG have been left in the code for
debugging purposes.
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these maps tend to be fairly long lived so it buys us nothing other than
code complexity.
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Since this means the necessary gtt alignment may change. Nothing did
this already, so all it does it allows the code to be simpler.
idea from Daniel Vetter.
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interrupt handler. So the locking and spl manipulation can simply go
away.
ok deraadt@, oga@
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that kills gtt mappings.
In both of these case we want all writes to hit the bus before we do
whatever we're about to do.
Doesn't solve any problems that I know of but it may help.
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When we disable tiling (for example whenever we free an object to out
userland cache), we stall the gpu so that we can get rid of the fence
register covering its bit of the gtt.
Instead, mark it as invalid and then free it on next use, leading to
less of a gpu stall if any. Leads to some slight performance improvement
on 8xx, 91x and 94x chipsets which are fence constrained.
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tag and compare the individual components.
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VGA device can be active, and is responsible for routing IO to the active VGA
device. Processes can use the new PCIOC_GETVGA and PCIOC_SETVGA ioctls
to manipulate the VGA arbiter.
ok deraadt@, oga@
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ok deraadt@
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sysctl.h was reliant on this particular include, and many drivers included
sysctl.h unnecessarily. remove sysctl.h or add proc.h as needed.
ok deraadt
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found by clang static analyser
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found by clang static analyser.
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Due to the messy context setup code this was breaking ipv6 forwarding
when ipv4 offloading was enabled. All checksum offloading remains
disabled for now.
Debugged with and ok claudio@
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we shouldn't be touching the config space at all here.
Found by the clang static analyser.
ok deraadt
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index
- we only care about unsolicited responses from the codec we're using
- no need to enable unsolicited responses until we know which codec
we're using
fixes crash reported by jacekm@
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The spec says this bit should always be set. It can help resolve
hardware deadlocks where a unit downstream of the VS is waiting for more
input, the VS has one vertex queueed up but not dispatched because it
hope to get one more vertex so it can dispatch a 2x4 block, and software
isn't handing any more vertices due to waiting on rendering.
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found by Clang static analyser.
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prevent the horrible constructs we use to determine generation
otherwise.
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The tiling check was insufficient and allowing too large pitches, which
in some cases could cause graphical corruption, strengthen the check so
that only valid values are used. Solved and patch ported from one by
Daniel Vetter on intel-gfx.
tested by Dorian Buettner (first dot last @ gmx dot de); thanks!
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written to detect the Intel RAID metadata format such that we no longer risk
overwriting it. If this makes you lose your disks, you'll need to change the
controller type from RAID to AHCI in the BIOS to get them back.
ok marco@, deraadt@
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when we go to pin, additionally check alignment against that required
for tiling and unbind/rebind if needed. We shouldn't hit this case, but
it is a good to check (would have found the bug in the last commit).
tested by mlarkin and matthieu (and myself, of course)
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alignment errors that matthieu and mlarkin saw.
Tested by both of them, and by me.
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retrying that will hurt.
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for it, oops.
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- support sharing a phy port by devices (should work fine with sas
expanders that share phy port number if such exist);
- remove dead timeout_xs stuff;
- make mpii_push_reply take a struct mpii_rcb argument instead of an
address (like mpi does);
- use SLIST instead of TAILQ to manage ccbs (ala mpi);
- rototil openfirmware attachment code as it was copied verbatim
(but with an error) from mpi and clearly wasn't tested;
- increase reset delay to 240ms for stability purposes;
- sprinkle some 'default' cases in a bunch of switch statements;
- remove several splbio's from the code that runs on boot;
- clarify/simplify the code that deals with sc_vd_id_low;
- some slight cleanup.
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Tested by me and mlarkin on amd64 and i386
ok oga
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a process instead of using curproc. ok deraadt
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pciide(4) needs to formward DVACT_SUSPEND and DVACT_RESUME events to its
children, so do that.
Gets rid of the nasty "click" sound from the disk on many laptops.
ok marco@, jsg@
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revision type.
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- support additional volume events;
- track volume rebuild progress;
- support for drive hotplug;
- log when volume state changes and when we start to resync;
- mpii_device handling rewrite (r/b tree is no more);
- improvements in mpii_ioctl_* functions;
- use internal disk_phys_num again as phy port number based
scheme was proven to be unreliable;
- fixup ioc_status check in mpii_scsi_cmd_done;
- change Offline state to Invalid when drive is gone;
- fixup recognition of the rebuilding state;
- don't leak ccb if poll fails;
- make use of the MPII_F_RAID flag and register with bio only
if there are RAID capabilities (idea from mpi);
- EVENT_UNMASK macro improvement from Kai Doernemann;
- use proper endianness when setting ccb_dev_handle;
- lower a polling delay in the mpii_complete;
- improve readability and debugging output in several places;
- change semantics of the SAS discovery event handler;
- start of the event cleanup;
- start of the whitespace cleanup;
- start of the KNF cleanup;
from Mike Belopuhov <mkb@crypt.org.ru>
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Manager api.
This is currently disabled by default under ifdef INTELDRM_GEM (option
INTELDRM_GEM in a kernel config or a patch to i915_drv.h needed to
enable), mostly because the intel X driver currently in tree does not
always play well with GEM and needs to be switched to UXA accelmethod
(which is the only option on later drivers).
While based on the intel drm code in the linux kernel this has come cleanups and
some obvious behaviour changes:
1) mmap through the GTT is entirely coherent with the gpu cache, removing
mappings whenever the cache dirties so you can not race with userland to write
to memory at the same time as the gpu.
2) pread/pwrite access is tiling-correct, so userland does not need to tile
manually (mesa has already been fixed for this a while ago). The straw that
broke the camels back here was the bit17 swizzling stuff on some mobile gpus
meansing that while userland did the swizzle itself, the kernel had to do
*extra* swizzling, this was frankly retarded so the option was dropped.
3) there is no option to map via the cpu from userland, again due to
coherency issues.
4) additional integer overflow checking in some areas.
5) we only support the newer EXECBUFFER2 command submission ioctl. the
old one is not supported at all (libdrm was fixed WRT over a week ago).
now the TODOs:
1) the locking is funky and is only correct due to biglock. it does
however work due to that. This will be fixed in tree, the design in
formulating in my head as I type.
2) there are currently no memory limits on drm memory, this needs to be
changed.
3) we really need PAT support for the machines where MTRRs are useless, else drm
uses quite a lot of cpu (this is a bug that continues from the older code
though, nothing new).
4) gpu resetting support on other than 965 is not written yet.
5) currently a lot of the code is in inteldrm, when memory management
comes to other chipset common code will be factored out into the drm
midlayer.
Tested on: 855 (x40), GM965 and 915 by me. 945 by armani@ and jkmeuser@,
gm45 by armani@ and marco@. More testing is needed before I enable this
by default though. Others also provided testing by what they tested
escapes me right now.
In order to test this enable INTELDRM_GEM in a kernel and add the following line
to the driver section in xorg.conf (I am working on a patch to autodetect the X
stuff):
Option "AccelMethod" "UXA"
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if supported.
When we do memory management on intel this would lead to a LOT of
wbinvd() to deal with gpu->cpu incoherency. no one wants that.
Needed for sanity of inteldrm memory management which is coming up next.
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