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path: root/sys/dev/sdmmc
AgeCommit message (Collapse)Author
2019-04-02Don't detach non-removable devices during resume on "sdhc* at acpi?".Stefan Sperling
Makes hibernate work with rootfs on built-in emmc storage. Tested on King Jim Portabook. ok deraadt@ kettenis@
2019-02-07Consistently use m_freem(9). This fixes possible leaks in a fewPatrick Wildt
error cases.
2019-02-04Turns out we do need to handle control messages that exceed MLEN, soMark Kettenis
allocate a cluster if the message is larger than that. Fixes a panic on shutdown on my Asus X205TA. ok patrick@, stsp@
2018-12-29Allow passing the maximum size of a segment that a SD/MMC hostPatrick Wildt
controller can handle for DMA tranfers, since not all support 64k. ok kettenis@
2018-12-22Avoid using m_trailingspace(9) on an mbuf allocated with MGET(9) as it reliesMark Kettenis
on header fields that aren't initialized, which may trigger an assertion. Check whether the control message doesn't exceed MLEN instead and turn the check into a KASSERT as the driver should not generate control messages that are larger. with help form claudio@ (who points out that the driver should not use MT_CONTROL here). ok patrick@
2018-11-09M_LEADINGSPACE() and M_TRAILINGSPACE() are just wrappers forClaudio Jeker
m_leadingspace() and m_trailingspace(). Convert all callers to call directly the functions and remove the defines. OK krw@, mpi@
2018-09-06Implement 64-bit DMA support in sdhc(4).Patrick Wildt
tested in snaps ok kettenis@
2018-08-09Implement out-of-band interrupt support in the bwfm(4) SDIO backend.Patrick Wildt
2018-08-09Allow passing per-function cookies through the SD/MMC bus to SDIOPatrick Wildt
devices. This allows SDIO device drivers to read information from the ACPI or FDT tables. ok kettenis@
2018-08-09Correct the bitmask that returns the function count. We missed a bitPatrick Wildt
and thus only supported 4 functions instead of 8. ok kettenis@
2018-07-24Add support fotr the BCM4335/4339 SDIO chip to bwfm(4). This one is a bitMark Kettenis
slow booting up, so give it a bit longer to enable the clock. ok patrick@
2018-07-17TX packets, which can be either Ethernet or control packets, must bePatrick Wildt
sent in order. Otherwise it is possible that the key is set before we send out the EAPOL packet, or that packets are sent out before the key is set. Thus modify the SDIO backend to put both types into the same internal TX queue, which will be sent asynchronously. Discussed with bluhm@
2018-07-16Add support for the BCM43455 SDIO chip to bwfm(4).Patrick Wildt
2018-07-16In certain modes SDIO-connected bwfm(4) chips might expect us to readPatrick Wildt
another packet (even though nextlen is set to none) to issue more RX interrupts.
2018-06-18Run the code to handle interrupts directly from the interrupt handlerMark Kettenis
instead of from a task. The sdmmc(4) interrupt handler is already executed in process context and returning from the interrupt handler without acknowledging the interrupts may lead to an interrupt storm. ok patrick@
2018-06-17Add curly braces to the if-condition to make sure the bus widthPatrick Wildt
is only bumped if the high-speed mode is available. ok kettenis@
2018-06-04in non-DIAGNOSTIC kernels, rw_assert_wrlock becomes a nop which leaves theTheo de Raadt
local variable dangling, so calculate the lock address by hand at invocation ok kettenis
2018-06-044-bit bus width is mandatory for SDIO cards that support High SpeedPatrick Wildt
mode, so switch from 1-bit to 4-bit bus width if the host controller supports it. ok kettenis@
2018-06-04Switch to SDIO High Speed mode if the host controller supports it.Patrick Wildt
ok kettenis@
2018-05-30Implement SDIO DMA support. This is achieved by wrapping thePatrick Wildt
sdmmc_io_rw_extended() function and loading the passed buffer using the bus dma API akin to the SDMMC memory card code. The 2-byte and 4-byte accessors continue to use PIO. ok kettenis@
2018-05-30For the upcoming SDIO DMA support we need to use DMA-able bufferPatrick Wildt
to send/receive data. This basically means that we cannot use any malloc(9)'d buffer. For this, use dma_alloc(9) to allocate a buf that can fit a whole SDIO frame (unfortunately without headers). Keep note that we need to round up the transfer sizes to block- sized (for TX packets) or 4-byte alignment, since some DMA con- trollers truncate the request size. If there's anything wrong, the KASSERTs will catch it. ok kettenis@
2018-05-30Clear the DMA select bits in case we use PIO instead of DMA. SomePatrick Wildt
SDHC controllers get confused if the ADMA bit is set even though we don't set the DMA enable flag. This can happen with the SDIO stack which uses PIO for 4 byte read/writes but DMA for larger transfers and thus switches from one mode to the other. ok kettenis@
2018-05-27BCM43430 SDIO works if we load the appropriate firmware.Mark Kettenis
ok patrick@
2018-05-26BCM4356 SDIO works if we load the appropriate firmware.Mark Kettenis
ok patrick@
2018-05-25So far the SDIO stack issued one transfer for every 64 byte to bePatrick Wildt
copied. This severely limits the speed over the bus. By using block mode we can issue block-sized transfers, which bumps the transfer size to at least 512 bytes. By using multi-block mode we can copy up to 511 blocks per transfer. ok kettenis@
2018-05-25For SDIO multi-blocks we must not use the AUTO CMD12 feature,Patrick Wildt
this is only for memory card read/writes. ok kettenis@
2018-05-24Release rwlock on bwfm(4) SDIO initialization error. Fixes hang foundPatrick Wildt
by florian@ when firmware isn't present initially.
2018-05-23Implement a separate initialization stage so that we can still usePatrick Wildt
and initialize bwfm(4) later in the case that the firmware was not available on bootup and was only later installed. ok stsp@
2018-05-23Extend list of supported bwfm(4) SDIO chips.Patrick Wildt
2018-05-21Make the way we print "not configured" lines for SDIO devices a bit nicer.Mark Kettenis
ok stsp@
2018-05-21Consistently suffix the pre-processed NVRAM binary that the bwfm(4)'sPatrick Wildt
firmware requires on SDIO-connected chips. From ketttenis@
2018-05-19Akin to the PCI attachment driver we can extract the chip's dmesg(8)Patrick Wildt
over the SDIO bus by accessing the correct addresses. This helped me find the RX FIFO overflow issue and might help find more issues where the chip's firmware complains about our wrongdoing.
2018-05-18After reading the first frame, which we can do in two reads (softwarePatrick Wildt
plus hardware header, which tell us the length of the following data), we can issue full packet reads. The software header contains a field that informs us of the full length of the next frame that we can read, so we can do that in a single sitting. This brings us down from three SDIO read invocation to a single one per packet for a given RX stream.
2018-05-17The Broadcom FullMAC firmware has a few ways of doing flow control. OnePatrick Wildt
of those is a sequence number based window mechanism. Essentially every packet on the SDIO bus has a sequence number. The chip records which sequence number we used last and when it sends us replies, it tells us the maximum sequence number it accepts. This means we can calculate a window of sequence numbers that we are allowed to use. With this I no longer overflow the chip's RX fifo and can do stable network transfers.
2018-05-16After having finished transmitting the last mbuf, don't just return toPatrick Wildt
the caller. Otherwise we skip restarting the ifq which means that if we ever have a full queue and go oactive, there is no coming back. So break out from the loop and call ifq restart if the queue is not full.
2018-05-16Implement a BCDC control packet mechanism based on the command requestPatrick Wildt
ids. So far we were only able to have one command in flight at a time and race conditions could easily lead to unexpected behaviour, especia- lly combined with a slow bus and timeouts. With this rework we send or enqueue a control packet command and wait for replies to happen. Thus we can have multiple control packets in flight and a reply with the correct id will wake us up.
2018-05-01Bump the clock frequency to a higher level that every card (per spec)Patrick Wildt
has to support for MMC cards prior to reading the extended registers. We already do this for SD cards. Fixes eMMC support on the i.MX8M. Tested by and ok kettenis@
2018-03-30Add some sensible error checking in the hibernate io path, helpfullyJonathan Matthew
suggested by coverity (via daniel@)
2018-03-20Add hibernate IO path for sdmmc(4). This requires some help from theJonathan Matthew
sdmmc chipset driver, currently only implemented in sdhc(4), but mostly uses the regular path. sdhc(4) also needed the ability to perform IO while cold. ok deraadt@
2018-03-19Make it possible for the sdhc(4) attachment glue to specify the base clockMark Kettenis
frequency. ok patrick@, visa@
2018-02-11Use the new APIs for setting block lengths and reading from/writing toPatrick Wildt
memory regions.
2018-02-11Add sdmmc_io_set_blocklen() which allows to set the block length of anPatrick Wildt
SDIO function. This is necessary for some SDIO cards that need to be talked with using smaller block lengths than the maximum supported by the host controller. ok kettenis@
2018-02-11Add sdmmc_io_read_region_1() and sdmmc_io_write_region_1() as anPatrick Wildt
interface for "reading memory" akin to the bus_space(9) API. The already existing multi interface is used for "reading FIFOs". The technical difference is that one always reads from the same address (FIFO) while the other increments the address while reading (memory). ok kettenis@
2018-02-11Since the BCDC header has a variable data offset, so the ethernet packetPatrick Wildt
alignment can be variable, it's better to move taking care of alignment into the BCDC receive code.
2018-02-11Update the packet header length as well as the mbuf length onPatrick Wildt
receive. Did that everywhere else but missed it here.
2018-02-10fix build with SDHC_DEBUG defined, no binary change otherwiseJonathan Matthew
2018-02-09Implement the bwfm(4) SDIO bus logic. This is the bus layer thatPatrick Wildt
converts the logic of the upper layers (sending control messages, sending data messages, receiving event or data messages) into the corresponding work that has to be done on the lowest layer. SDIO is not the fastest bus for exchanging network packets, but maybe there is room for tuning. Actual TX/RX is being done in a worker task that serializes access to the hardware. This is good enough to attach to WiFi networks and do network transfers. Developed and tested on a Cubox-i.
2018-02-07Outsource setting the backplane window into a specific function so itPatrick Wildt
can be called and reused in different places.
2018-02-07Move SDIO bus and protocol definitions from the shared headerPatrick Wildt
into one header specific to the SDIO attachment driver. Also add more register and protocol definitions to it.
2017-12-24Allow SD/MMC controller drivers to allocate their own DMA mapping structureMark Kettenis
to account for any relevant hardware constraints. ok stsp@
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