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path: root/sys/dev/usb/xhci.c
AgeCommit message (Collapse)Author
2022-07-15Use a separate varaible to signal a "dead" controller (that has disappearedMark Kettenis
from the bus, probably because of hot(un)plugging it). This makes sure that we still ack interrupts that arrive while the controller is "dying" (when we go down into suspend or if an unrecoverable hardware error occurs). Fixes an interrupt storm when we suspend on Amlogic arm64 boards. ok deraadt@
2022-04-12constify USB host controller method tables and root hub descriptorsChristian Weisgerber
ok mglocker@
2022-01-09spellingJonathan Gray
feedback and ok tb@ jmc@ ok ratchov@
2021-11-22Align memory allocation for USB device drivers and USB HC drivers:Marcus Glocker
* USB device drivers use M_USBDEV instead of M_DEVBUF. * USB HC drivers use M_USBHC instead of M_DEVBUF. In a vanilla setup, this enlarges the USB memory pool. ok anton@
2021-10-26Improve unhibernate performance (30% on some machines, another upcoming diffTheo de Raadt
shows gains up to 50%) by skipping attach of irrelevant devices, which are tagged CD_SKIPHIBERNATE in the per-driver cfdriver. In particular, usb devices are not attached, so they don't need to detach during the suspend-unpack-resume. New bootblocks are required (which tell the kernel it's job is unhibernate before configure runs) tested by various
2021-02-24remove unused xhci_cmd_evaluate_ctx()Jonathan Gray
ok mpi@
2020-12-24Do proper accounting of zero length TDs. Currently a specific numberMarcus Glocker
of zero length TDs can cause our free TRBs to run out, causing xhci(4) to return USBD_NOMEM to the USB stack. The issue was reported by Jonathon Fletcher <jonathon.fletcher () gmail ! com> -- Thanks! Reviewed/suggestions by patrick@. ok mpi@
2020-07-31In xhci_device_isoc_start() do first check if the transfer isMarcus Glocker
in-progress before we do check for the pipe being halted. This fixes some kind of race condition for isoc devices during device close when xp->halted gets set while usbd_start_next() still tries to dequeue in-progress transfers which will report 'usbd_start_next: error=13' (USBD_IOERROR). ok mpi@
2020-07-29Don't nest a enum declaration inside a struct declaration, and anywayTheo de Raadt
since the enum isn't tied to the type (because want smaller storage) is better to use #define ok kettenis mglocker
2020-07-28Fix a problem related to isochronous transfers appearing in certainMarcus Glocker
constellations resulting in bogus frame sizes being returned by xhci(4). E.g. for uvideo(4) devices erroneous video streams were reported. The problem occurs when multi-trb TDs are queued and being processed as a zero-length or short transfer. Those cases were not handled in the current isochronous code path, which this patch is adding. Feedback and testing done by many on tech@. Thanks! ok mpi@
2020-06-30When a transfer times out, the TRB should be aborted, too. But stillGerhard Roth
the completion interrupt may already be pending while aborting. Hence, in xhci_event_command() ignore events from a TRB that is not the expected one. And don't let xhci_abort_command() yield the CPU. ok mpi@
2020-06-24Acknowledge xhci(4) interrupts before calling usb_schedsoftintr().Patrick Wildt
On powerdown (halt -p), sd(4)'s suspend function tries to powerdown a USB mass storage using a STOP command. In that case we are already cold and splhigh(), so that the xhci is supposed to run in polling- mode. usb_schedsoftintr() behaves differently when running in polling-mode. Instead of scheduling a soft interrupt, it immediately dequeues from the event queue. But dequeueing means touching the xhci registers. Apparently we need to acknowledge the interrupts before touching those registers, the hardware doesn't like it otherwise and we will never get an interrupt status for the second transfer. ok gerhard@
2020-04-03Move the responsibility of syncing the data buffers from the USBPatrick Wildt
stack into the USB controller driver, since not all of the xfers actually use DMA and some invalidations might even be harmful. The important part is to sync before handing the buffer to the controller, and to sync on a successful transfer before handing it back to the USB stack. For isoc transfers it's easier to sync the complete length of the transfer, since the buffer to flush is not filled in a contiguous fashion. For dwc2 there's a common point which takes care of the start of transfers from or to devices, where we can make sure that our buffers are synced. On completion, there's a common point before handing it off to the USB stack. For ehci there are three places which take care of the start of transfers from or to devices, where one already does the sync, while the two other places still need the sync. There are two completion handler (isoc and non-isoc), where one already has a comment asking for the need of a sync. The done handler for intr xfers does a sync that is not needed anymore after adding the sync in the completion handler. For ohci there are three places which take care of the start of transfers from or to devices, where all of them were still in need of the sync. For completion, there is one place for isoc xfers and two places for handling successful generic xfers. For uhci there are two places which take care of the start of transfers from or to device, where all of them were still in need of the sync. For completion, there is one handler for both isoc and non-isoc xfers where syncs need to occur. For xhci there are three places which take care of the start of transfers from or to device, where all of them were still in need of the sync. For completion, there is one handler for isoc and one for non-isoc xfers where syncs need to occur. With this we can revert the workaround that implicitly allocated buffers are COHERENT, since now control transfers fulfilled by the driver code (instead of the controller doing DMA) are not flushed into oblivion anymore. Tested by Janne Johansson with dwc2 (octeon) Tested by kettenis@ with xhci(4) (octeon) Tested by patrick@ with ehci(4) on a Cubox-i (armv7) Tested by patrick@ with xhci(4) on an i.MX8MQ (arm64) Tested by tobhe@ with dwc2 on a rPi 3b (arm64) ok kettenis@
2020-03-02Fix endian swapping of trb_flags and trb_status in xhci(4).Visa Hankala
This corrects computation of xfer->actlen, allowing xhci(4) to work again on octeon and other big endian architectures. Reported by Allen Smith OK patrick@
2020-02-22use the UE_GET_XFERTYPE macro where applicableJasper Lievisse Adriaanse
ok mpi@
2020-01-22Add a zero length TD, rather than adding a zero length TRB to theKenneth R Westerback
original TD, when a transfer is a multiple of the max packet size. The zero length TD will have a NULL xfer pointer. As a result "NULL xfer pointer" situations become perfectly normal. So change the log_warnx() that issues that verbiage to a log_debug(). Note that the original transfer will complete and report its result up the USB stack before the zero length transfer is executed. Fixes (at least) urtwn(4) interfaces. Feeback, cluebats, fixes and ok patrick@
2020-01-13Ensure XHCI_SCTX_DCI() always contains a valid number, i.e. the DCI ofKenneth R Westerback
the highest active endpoint context. Don't zap other fields when setting XHCI_SCTX_DCI(). Fixes (at least) Etron EJ168 USB 3.0 Host Controllers vs USB 2 devices. Inspired by hselasky FreeBSD revision 243780. Feedback from kn@, ok beck@ (previous iteration) patrick@
2019-11-28On short transfers with multiple TRBs in a TD we get two events.Patrick Wildt
One on the TRB that went short, and one for the last TRB in a TD. We already set actlen only once so that the last TRB in a TD does not override it, but some controllers throw another short event instead of a success event, so we have to add the same check there as well. ok gerhard@ mglocker@
2019-11-18Fix off-by-one TRB issue in bulk transfers larger than 64k.Marcus Glocker
This makes udl(4) on xhci(4) work fine. Help and ok patrick@
2019-11-18Fix actual length calculation of short transfers in xhci(4). So farPatrick Wildt
we have subtracted the remaining length from the total transfer length, which essentially means that we assume that all TRBs have successfully been transferred apart from the remainder. Actually we might get a short completion in the middle of a chain of TRBs, which means that all TRBs until this TRB have completed successfully apart from a remainder. Thus we have to count the length of all TRBs until and including the one that we went short on, and remove the remainder. All following TRBs in the same transfer must be ignored. Found by and fixed with gerhard@ ok mglocker@
2019-10-06Use MSEC_TO_NSEC() to define XHCI_CMD_TIMEOUT & use it w/ tsleep_nsec(9).Martin Pieuchot
ok visa@, kn@
2019-06-13Do not consider the pipe as halted if the device is gone.Martin Pieuchot
Analysed by and ok claudio@
2019-05-21Fix NULL check with wrong pointer in xhci_event_xfer_isoc(); CID 1480287Stefan Sperling
ok ratchov@
2019-04-30Decrease verbosity when XHCI_DEBUG is defined.Alexandre Ratchov
ok mpi
2019-04-10Handle missed service errors, specific to isochronous transfers.Alexandre Ratchov
After each MSE, ensuire usbd_complete_transfer() is called for each missed transfer, for which there's no transfer completion event. Fixes crashes and deadlocks in upper layers caused by the missing completion. ok deraadt, patrick; help from mpi, patrick, gmlocker
2019-03-17Since an isoc endpoint never halts, move to remaining error handlingMarcus Glocker
code in xhci_event_xfer() to the generic handler function. suggested and ok mpi@
2019-03-17Move the handler code in the xhci_event_xfer() switch case in two separateMarcus Glocker
functions for isoc and !isoc xfers. Suggested by mpi@. ok patrick@, stsp@
2019-03-17Remove obsolete semicolon at end of case switch.Marcus Glocker
2019-03-16Merge the duplicate code to handle isoc SHORT and SUCCESS xfer eventsMarcus Glocker
to one single function. ok mpi@
2019-03-15Improve and enable isochronous transfers in xhci(4). Each isochronousPatrick Wildt
frame has to be enqueued as Transfer Descriptor. This means each frame starts with an isoch TRB and may also contain further normal TRBs. The TDs each throw at least one interrupt for a successful completion or possibly more in case of a short xfer. We have to account the amount of data transfered for each frame using the completion of the matching TD and its TRBs. Thanks to stsp@ for initiating this, and many more thanks to mglocker@ for reworking and cleaning up my initial diff. Further improvements can happen in-tree now. Tested by mglocker@, phessler@ and stsp@ ok mglocker@, stsp@
2019-03-15The max burst size that is encoded in wMaxPacketSize is zero based,Patrick Wildt
as in: Since there's always one transfer, 0 means 1. Thus we have to add 1 (not OR) to get to the desired number. ok mglocker@ mpi@ stsp@
2019-03-12Fix typo in debug print: wih -> withPatrick Wildt
ok mpi@
2019-03-11Add missing bus powered bit, from aalm@Martin Pieuchot
2019-03-01Since ring->index points to the next free slot, once we reach index zeroPatrick Wildt
we know that the last non-link TRB has been written and we can look at the flags to set the chain bit in the link TRB. Since we will now toggle the cycle bit on the first TRB of a ring, set it on the ring reset. Tested by jcs@, jsg@ and visa@ "commit it" jcs@
2019-02-27Make xhci_ring_produce() check the previous TRB to find out if itPatrick Wildt
needs the Chain Bit set or not instead of using the last parameter, which is used to mark the last TRB in a USB transfer, not in a TD. To make that work we need to setup the recently acquired TRB before calling xhci_xfer_get_trb() the next time. Thus setting up the initial TRB has to happen right away. To kick the transfer off we simply flip the toggle bit on the first TRB right at the end. Fixes regression for jcs@, dhill@ and stsp@ Initially discussed with mpi@ ok stsp@
2019-02-21Transfers that span multiple TRBs which wrap around the ring andPatrick Wildt
thus have the Link TRB inbetween must have the Chain Bit set in the Link TRB. Otherwise xHCI controllers might think that the transfer ends at that point. Fixes an issue that was most prominently seen as Invalid CSW error when using umass0 on octeon and i.MX8M. Tested by visa@ ok mpi@
2019-02-01Print xhci version in hex, from sc.dying at gmail.Martin Pieuchot
2018-09-06If we cannot stop the endpoint when aborting a transfer assume thatMartin Pieuchot
the device is gone and give back the descriptor to the stack. Without this usbd_abort_pipe() could end up in an infinite loop. Issue reported by Tom Murphy.
2018-09-05Serialize synchronous commands with a rwlock.Martin Pieuchot
Prevent triggering an assert if two drivers try to submit a command at the same time. Issue reported by Tom Murphy.
2018-07-16typos, from Michael W. Bombardieri.Martin Pieuchot
2018-05-13Add bus DMA barriers to ensure the hardware does not see a TRB cycle bitVisa Hankala
flip before the rest of the TRB is updated. OK dlg@, pirofti@, mpi@
2018-05-08Print xHCI revision in dmesg.Martin Pieuchot
ok patrick@, kettenis@
2018-04-29Unsigned values are always >= 0, fix Coverity 1468443.Martin Pieuchot
2018-04-28Print more debug informations in the event xfer handler.Martin Pieuchot
2018-04-27Introduce an helper function to extract endpoint's max burst value.Martin Pieuchot
Use this helper to calculate the Transfer Burst Count (TBC) and Transfer Last Burst Packet Count (TLBPC) required for isochronous support. Note that SS companion descriptors are still not read. While here print the ETE and IST values in debug mode.
2018-04-27Print index as unsigned.Martin Pieuchot
2018-04-27Fix an off-by-one in xhci_xfer_tdsize().Martin Pieuchot
While here use UE_GET_SIZE() coherently. ok pirofti@, stsp@, visa@
2018-04-26Reduce differences between isoch & bulk/intr routines.Martin Pieuchot
ok stsp@
2018-04-26Follows section 6.2.3.6 to compute endpoint interval.Martin Pieuchot
ok stsp@
2017-09-08Add support for isochronous transfers to xhci(4).Stefan Sperling
This is just a step forward which allows further progress to happen in-tree. The isochronous code path remains disabled for now. Playing audio over xhci(4) does not work properly yet, and I haven't even tested video input. Based on a work-in-progress diff by mpi@ from 2015. ok mpi@
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