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enabled (it is not enabled yet.)
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and they don't make any sense (the old deprecated GCC way of marking noreturn
functions is surely not what was meant here).
ok jsg@, guenther@, marco@
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disks on ATI SBx00 care is mysterious but let's keep them working.
Fix tested by Josh Elsasser, submitter of PR#6365. Thanks!
ok dlg@
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actually do so).
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- pmap_kremove takes a va and a size, not a va range (unlike pmap_remove,
that gratuitious difference is nothing if not annoying).
- fix a memory leak of the bit 17 bitstring.
- fix the offset calculation when iterating through the dma segments.
Tested by Brandon Mercer, his machine now seems to be rock solid.
Remember kids, if a code path has not been tested fully, it does not work!
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This was causing swizzling on bit 17 swizzling intel IGDs when not
needed. Thanks to Brandon Mercer for testing.
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pointed out by Clang static analyser.
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the one changed.
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while (condition) {
do_stuff()
increment_condition /* this was missing */
}
To a for loop like it always should have been. I have no idea what I was
smoking when I wrote this function.
Fixes the crash on hardware that does bit 17 swizzling (turns out the
three I know of are all 945s) as soon as we first unbind an object.
Thank you very much to Brandon Mercer for actually managing to get me a
crash dump so i could debug this, and also for testing the fix.
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Makes gcc4 happier.
ok deraadt@, marco@
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webcam.
ok mglocker
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libdrm bug recently.
Correct to what was intended.
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accessed by the gpu or needing a flush). Since this implies that the object is
wanted, emit the flush then to save time.
Makes things a lot smoother than before in some GL applications, since
before we were claiming that object needing a flush were unbusy so the
next map stalled the gpu waiting on a flush.
From daniel vetter on intel-gfx.
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conflicts.
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If we just read access to some data that has been accessed by the gpu,
only sleep until the end of the gpus last write (which we track). So
instead of stalling the gpu until the last time accessed, both can read
at the same time (which is allowed and coherent as long as the right
invalidation happens).
Since we check offsets from userland before we exec a batchbuffer, this
helps 965 (with lots of read only relocations in the render path) quite
a lot.
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Before, as well as being kinda nasty there was a very definite race, if
the last reference to an object was removed by uvm (a map going away),
then the free path happened unlocked, this could cause all kinds of
havoc.
In order to deal with this, move to fine-grained locking. Since uvm
object locks are spinlocks, and we need to sleep in operations that will
wait on the gpu, provide a DRM_BUSY flag that is set on a locked object
that then allows us to unlock and sleep (this is similar to several
things done in uvm on pages and some object types).
The rwlock stays around to ensure that execbuffer can have acces to the
whole gtt, so ioctls that bind to the gtt need a read lock, and
execuffer gets a write lock. otherwise most ioctls just need to busy the
object that they operate on. Lists also have their own locks.
Some cleanup could be done to make this a little prettier, but it is
much more correct than previously.
Tested very very vigorously on 855 (x40) and 965 (x61s), this found numerous
bugs. Also, the I can no longer crash the kernel at will.
A bunch of asserts hidden under DRMLOCKDEBUG have been left in the code for
debugging purposes.
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these maps tend to be fairly long lived so it buys us nothing other than
code complexity.
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Since this means the necessary gtt alignment may change. Nothing did
this already, so all it does it allows the code to be simpler.
idea from Daniel Vetter.
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to pad-align the size of the structure; it grows, the disklabel ioctl's are
break ABI. Change the uid to a character array. this also simplifies some
other stuff
ok jsing
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interrupt handler. So the locking and spl manipulation can simply go
away.
ok deraadt@, oga@
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oga@.
ok deraadt@
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that kills gtt mappings.
In both of these case we want all writes to hit the bus before we do
whatever we're about to do.
Doesn't solve any problems that I know of but it may help.
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When we disable tiling (for example whenever we free an object to out
userland cache), we stall the gpu so that we can get rid of the fence
register covering its bit of the gtt.
Instead, mark it as invalid and then free it on next use, leading to
less of a gpu stall if any. Leads to some slight performance improvement
on 8xx, 91x and 94x chipsets which are fence constrained.
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identifier, allowing the disk to be identified without relying on the
device name.
ok deraadt@ krw@ beck@ marco@ todd@
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SCSI when you're talking to a scsi to ata translation layer (satl). this
implements the ata command ioctl handler in scsi_ioctl.c that wraps the
ata command requests up in these scsi commands and then issues them against
the hardware. this cuts atascsi over to interpreting these scsi commands
rather than the ioctls directly.
this should allow mpi users (with a relatively recent firmware) to use
atactl against their SATA disks. i cant test cos my mpi(4) parts are too
old to either support these scsi commands or too old to take recent
firmwares.
ok marco@ @krw tested by krw@ and me on ahci/atascsi
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ok deraadt@
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ok sthen
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ok dlg@, marco@
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