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of new fields in the future is less disruptive. This is done similar
to how struct proc is handled for ps(1). ok jmc (man page changes)
tested fkr simon, and more suggestions from millert
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but defer the remainder of their initialisation until after the other devices
on their PCI bus have attached. This ensures that any USB2 controller has also
completed its initialisation before we start to initialise the USB1 parts.
This minimises the chance that a nasty SMM implementation will trash the USB1
controller's config when it performs legacy emulation handover of the USB2 part.
This time without accidentally leaving the OHCI controller shutdown, and with
some cosmetic fixes.
ok dlg@, OHCI tests mglocker@
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Save SOF (frame timing adjustment) before the very first host controller
reset, rather than at suspend/resume, otherwise any BIOS inserted value
is lost immediately.
ok dlg@
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Wait the stable power delay on a USB hub only once per hub (not per port),
and defer the delay for root hubs until the host controller event thread
starts, permitting some concurrency. Speeds up the boot process dramatically
when you have lots of host controllers.
ok dlg@
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This includes a nasty hack to reduce openings and throw away command slots
if the device supports a lower queue depth than the host controller does.
Yes, we're thinking about a better solution.
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silicon image 3124/3132/3531 sata chipsets eventually.
so far this is the autoconf glue, an actual match routine for the 3124, and
interrupt establishment code. it is split up between pci and ic cos there
are cardbus variants of these controllers that we can support in the
future.
thanks to jolan@ for the name, it was better liked than my initial
suggestion of siisl(4).
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don't use xa->flags afterwards.
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generation of interrupts when they arrive.
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Because you cannot have NCQ commands active at the same time as standard
(non-queued) commands, we must introduce a queueing scheme into the driver.
This scheme ensures that a standard command is only issued to the drive when
all currently active NCQ commands have finished, and that NCQ command issue
is delayed when we have a pending standard command.
Additionally, the queueing scheme adds a constraint to ensure that there are
never more than two standard commands issued on a port at once. This should
ensure that commands become active in the order they were submitted (regardless
of their command slot number) both initially and when the port is reactivated
after error recovery.
These points mean that issuing a standard command effectively serialises the
port, which may help us implement meaningful I/O barriers in the future.
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JMB368 supported for now, multi port cards
that share PATA/SATA need to do a complicated
internal channel mapping dance I plan to look into next.
ok grange@
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seeing things attach to the scsibus.
ok pascoe@
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it a bit easier to read. there are variations on this, but they can be
defined later.
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reset with during error recovery. Also, ensure that that CCB has been
stopped on the chip before putting it back in the pool.
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set and clear the device's MAC filter.
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No exceptions.
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`sort of ok' marco (before lock)
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could pick up a previous ATA_F_POLL from a previous non-data command.
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Note that the ATA spec says we're should retry after error until we see no
more errors. This is not (yet) implemented.
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error handling.
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isn't sent to the device.
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always return ATA_COMPLETE in the polled transfer case. Also, respect the
passed in timeout value when polling.
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these since last year, but i didnt see the point till the code would be
useful anywhere.
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something really big. The SCSI layer isn't yet ready for it.
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in the inquiry error paths, as the HBA will have already completed the
ata_xfer with an error.
Reminder and ok dlg@
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etc, just work.
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For those people who have reported about broken MAC address at attach
time, this should fix the problem.
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so that atascsi can deal with it.
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resetting it and stuff to avoid garbled dmesg output; found on some arm
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of the wdcreg.h include in atascsi.
"feel free to remove" pascoe@
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before we enable AHCI, so enable it before resetting saved capabilities.
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etc), and request that the D2H FIS at the completion of all (DMA) commands
generate an interrupt.
This makes each data transfer generate one interrupt instead of two and
should guarantee that the interrupt that is generated actually arrives
after the command has completed.
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works.
From dlg@
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simply include a pointer to the command FIS that we will issue to the device.
Include another space where we can copy back an error register set from a
failed command.
This means that we can now build and issue arbitrary commands from atascsi,
and retrieve errors back.
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atascsi will be driving, and add it to the AHCI CCB.
This effectively gives us all the resources we need for a transfer in one
hit, meaning that we don't need to worry about whether we will have a pool
shortage or not enough CCBs. The SCSI mid layer should take care to never
exceed the number of CCBs we have available, based on our sc_link.openings.
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From tbert <bret.lambert@gmail.com>
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