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webcam.
ok mglocker
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libdrm bug recently.
Correct to what was intended.
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accessed by the gpu or needing a flush). Since this implies that the object is
wanted, emit the flush then to save time.
Makes things a lot smoother than before in some GL applications, since
before we were claiming that object needing a flush were unbusy so the
next map stalled the gpu waiting on a flush.
From daniel vetter on intel-gfx.
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conflicts.
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If we just read access to some data that has been accessed by the gpu,
only sleep until the end of the gpus last write (which we track). So
instead of stalling the gpu until the last time accessed, both can read
at the same time (which is allowed and coherent as long as the right
invalidation happens).
Since we check offsets from userland before we exec a batchbuffer, this
helps 965 (with lots of read only relocations in the render path) quite
a lot.
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Before, as well as being kinda nasty there was a very definite race, if
the last reference to an object was removed by uvm (a map going away),
then the free path happened unlocked, this could cause all kinds of
havoc.
In order to deal with this, move to fine-grained locking. Since uvm
object locks are spinlocks, and we need to sleep in operations that will
wait on the gpu, provide a DRM_BUSY flag that is set on a locked object
that then allows us to unlock and sleep (this is similar to several
things done in uvm on pages and some object types).
The rwlock stays around to ensure that execbuffer can have acces to the
whole gtt, so ioctls that bind to the gtt need a read lock, and
execuffer gets a write lock. otherwise most ioctls just need to busy the
object that they operate on. Lists also have their own locks.
Some cleanup could be done to make this a little prettier, but it is
much more correct than previously.
Tested very very vigorously on 855 (x40) and 965 (x61s), this found numerous
bugs. Also, the I can no longer crash the kernel at will.
A bunch of asserts hidden under DRMLOCKDEBUG have been left in the code for
debugging purposes.
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these maps tend to be fairly long lived so it buys us nothing other than
code complexity.
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Since this means the necessary gtt alignment may change. Nothing did
this already, so all it does it allows the code to be simpler.
idea from Daniel Vetter.
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to pad-align the size of the structure; it grows, the disklabel ioctl's are
break ABI. Change the uid to a character array. this also simplifies some
other stuff
ok jsing
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interrupt handler. So the locking and spl manipulation can simply go
away.
ok deraadt@, oga@
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oga@.
ok deraadt@
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that kills gtt mappings.
In both of these case we want all writes to hit the bus before we do
whatever we're about to do.
Doesn't solve any problems that I know of but it may help.
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When we disable tiling (for example whenever we free an object to out
userland cache), we stall the gpu so that we can get rid of the fence
register covering its bit of the gtt.
Instead, mark it as invalid and then free it on next use, leading to
less of a gpu stall if any. Leads to some slight performance improvement
on 8xx, 91x and 94x chipsets which are fence constrained.
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identifier, allowing the disk to be identified without relying on the
device name.
ok deraadt@ krw@ beck@ marco@ todd@
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SCSI when you're talking to a scsi to ata translation layer (satl). this
implements the ata command ioctl handler in scsi_ioctl.c that wraps the
ata command requests up in these scsi commands and then issues them against
the hardware. this cuts atascsi over to interpreting these scsi commands
rather than the ioctls directly.
this should allow mpi users (with a relatively recent firmware) to use
atactl against their SATA disks. i cant test cos my mpi(4) parts are too
old to either support these scsi commands or too old to take recent
firmwares.
ok marco@ @krw tested by krw@ and me on ahci/atascsi
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ok deraadt@
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ok sthen
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ok dlg@, marco@
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and makes the ioctl path more reliable on busy disks by allowing it to
sleep in the runqueue for an io to use.
mk@ did the original diff and figured most of the problems out. ok mk@
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tag and compare the individual components.
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VGA device can be active, and is responsible for routing IO to the active VGA
device. Processes can use the new PCIOC_GETVGA and PCIOC_SETVGA ioctls
to manipulate the VGA arbiter.
ok deraadt@, oga@
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ok deraadt@
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sysctl.h was reliant on this particular include, and many drivers included
sysctl.h unnecessarily. remove sysctl.h or add proc.h as needed.
ok deraadt
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slipped into the original NetBSD code around sixteen years ago.
Although it has been working so far because some devices used
address zero and other devices ignored the wrong higher bits.
- Remove the mem_ring override in ne2000_attach() now that
dp8390_config() calculates mem_ring correctly.
From NetBSD, via brad
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chip initialization values (SCNTL0, DMODE, DWT, CTEST7).
No functional change on hppa; required by another upcoming attachment.
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found by clang static analyser
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found by clang static analyser.
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Due to the messy context setup code this was breaking ipv6 forwarding
when ipv4 offloading was enabled. All checksum offloading remains
disabled for now.
Debugged with and ok claudio@
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we shouldn't be touching the config space at all here.
Found by the clang static analyser.
ok deraadt
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index
- we only care about unsolicited responses from the codec we're using
- no need to enable unsolicited responses until we know which codec
we're using
fixes crash reported by jacekm@
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fixes TX power settings for CCK rates on AR9280 devices in
open-loop power control mode.
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The spec says this bit should always be set. It can help resolve
hardware deadlocks where a unit downstream of the VS is waiting for more
input, the VS has one vertex queueed up but not dispatched because it
hope to get one more vertex so it can dispatch a 2x4 block, and software
isn't handing any more vertices due to waiting on rendering.
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found by Clang static analyser.
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prevent the horrible constructs we use to determine generation
otherwise.
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The tiling check was insufficient and allowing too large pitches, which
in some cases could cause graphical corruption, strengthen the check so
that only valid values are used. Solved and patch ported from one by
Daniel Vetter on intel-gfx.
tested by Dorian Buettner (first dot last @ gmx dot de); thanks!
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