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firmware requires on SDIO-connected chips.
From ketttenis@
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controller. Some BIOSen deliver them to us in D3.
Override card detect if ACPI says that the child devices are non-removable.
ok mlarkin@
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ok mlarkin@
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a TI part (SND9039) but the datasheet is only available under NDA because it
contains "Intel proprietary information".
Initial implementation handles the thermal sensors, providing data to acpi(4)
which is used by acpitz(4). Power management functionality will be added
later. Disabled for now until some bugs in dwiic(4) are fixed.
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ok mlarkin@
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ok mpi@
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ok mlarkin@
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over the SDIO bus by accessing the correct addresses. This helped
me find the RX FIFO overflow issue and might help find more issues
where the chip's firmware complains about our wrongdoing.
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ok mlarkin@
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plus hardware header, which tell us the length of the following data),
we can issue full packet reads. The software header contains a field
that informs us of the full length of the next frame that we can read,
so we can do that in a single sitting. This brings us down from three
SDIO read invocation to a single one per packet for a given RX stream.
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No real change because we'll never run out of ccbs that early.
Noticed during review of the preceding changes.
ok dlg@
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work was done by Naoki Fukaumi, some tweaks and adjustment to match the
preceding changes by me. Tested on SAS2208, SAS3008, SAS3108, SAS3508.
ok dlg@
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case. Based on a diff from Naoki Fukaumi. We decided to keep using scsi
flags rather than switching to MFII_DATA_IN/OUT (as done in mfi(4)) so
callers can include SCSI_NOSLEEP if required.
ok dlg@
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debug output to use them.
ok dlg@
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Investigation by Naoki Fukaumi determined that this is
necessary on some controllers and works on all of them.
Tested on SAS2208, SAS3008, SAS3108, SAS3508.
ok dlg@
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of those is a sequence number based window mechanism. Essentially every
packet on the SDIO bus has a sequence number. The chip records which
sequence number we used last and when it sends us replies, it tells us
the maximum sequence number it accepts. This means we can calculate a
window of sequence numbers that we are allowed to use. With this I no
longer overflow the chip's RX fifo and can do stable network transfers.
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pointed out by stsp@
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ok mlarkin@
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Tested by Daniel Wade, <Daniel2 ! Wade at ge ! com>, thanks!
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ok mlarkin@
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accessed using the Chipcommon core anymore.
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which is shared with IPMI on HPE DL20 Gen9, its link state became down
a while or never became active again.
diff from FreeBSD through Naoki Fukaumi.
https://svnweb.freebsd.org/base?view=revision&revision=248226
ok mpi dlg
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Add the PLX PEX 9733 PCIe switch.
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the caller. Otherwise we skip restarting the ifq which means that if
we ever have a full queue and go oactive, there is no coming back. So
break out from the loop and call ifq restart if the queue is not full.
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instead of having imxccm(4) map more than it should and access the
memory space that imxanatop(4) should be responsible for.
ok kettenis@
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Discussed with kettenis@
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development in 2013. Registers are to be accessed byte-wise. The
command buffer, used to transfer the register index we want to access
on the chip, is not only used on write operations, but also on read
operations. Thus it has to be pulled into the main i2c exec method.
Since these are two transfers, we have to set "repeat start" and wait
for busy to be set. Some machines have a clock-frequency attribute on
the controller node which controls the speed (e.g. 400 kHz instead of
100 kHz).
ok kettenis@
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ids. So far we were only able to have one command in flight at a time
and race conditions could easily lead to unexpected behaviour, especia-
lly combined with a slow bus and timeouts. With this rework we send or
enqueue a control packet command and wait for replies to happen. Thus
we can have multiple control packets in flight and a reply with the
correct id will wake us up.
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Based on my original diff committed in if_iwm.c r1.171, with bugs fixed.
Fixes bogus "unhandled firmware response" errors on 8265 reported by mlarkin@
Tests by mlarkin@, benno@, matthieu@, anton@, kn@, Tracey Emery, Jesper Wallin
on 7260, 7265, and 8265 chips.
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ok visa@, patrick@
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"IC types" that identify Elantech-V4 touchpads.
Thanks to Ryan Lennox for help and testing.
ok mpi@
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flip before the rest of the TRB is updated.
OK dlg@, pirofti@, mpi@
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The only place where it was modified after initialization is a corner
case where the vnode of an open file is substitued by another one. Sine
the type of the file doesn't change, there's no need to overwrite `f_ops'.
While here proctect file counters with `f_mtx'.
ok bluhm@, visa@
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ok patrick@, kettenis@
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purposes can be enabled and disabled by WSMOUSEIO_SETPARAMS
requests.
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hardware registers. On Rockchip hardware it seems the address latches into
the filter logic only after writing writing the "low" register.
Fixes the Gigabit Ethernet interface on the Rockchip RK3328 and RK3399.
ok visa@, patrick@
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of fdt-enabled platforms in sync.
OK deraadt@
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bump to 400 MHz for the eMMC on i.MX8MQ.
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ok kettenis@
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values are defined in the device tree and make sure that all clocks
needed for controller and driver operation are configured as expected.
This allows modifying a clock's rate and parent. For now expect that
a parent clock is on the same controller as the muxed one.
ok kettenis@
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scrollback. Fixes use of an uninitialised attribute value in scrollback.
Patch from miod@ ok kettenis@
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