Age | Commit message (Collapse) | Author |
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Using this much memory may have negative side effects, but at least now
you have the option. Here's some rope; have fun.
maybe ok a few people.
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lowest bowels of the exception handling code, rather than in trap(). They
won't get recorded in the trap history, but there is a measurable speedup.
No change for non-CPU_R4000 kernels.
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so remove the former and include the latter instead of pulling it
in <dev/pci/agpvar.h>. This header already requires various other
types anyway. While here remove unneeded headers.
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such case loouput() is called not ether_output().
ok claudio@, mikeb@
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dropping the pcred argument. Fix handling of kill(-1, sig) from a
thread other than the original thread.
ok deraadt@
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Tweak the handling of ktrace EMUL when changing ktracing: only
generate one per process (not one per thread) and pass the correct
proc pointer down to the VFS layer. Permit generating of NAMI and
CSW records inside ktrace(2) itself.
ok deraadt@ millert@
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because USB_START_ADDR is defined to 0 and the softc is M_ZERO'd,
assume that root hubs are the only devices with a depth of 0.
Root hubs can now happily be detached and reattached.
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is included by a lot of files.
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rings, and rewrite all the addresses in the registers.
While here don't keep a copy of our usb(4) child device, autoconf(9)
knows how to reach our children.
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ok jmatthew@
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jmatthew@ agrees with me
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ok jmatthew@
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being 4 byte aligned.
rewrite qle_put_data_seg so it takes an address and length rather than
a dma descriptor so it can be used to write sges for arbitrary things
rather than just dmamaps. use it to write out all sges.
ok jmatthew@
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extra restrictions on ordering.
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the inclusion of <dev/systrace.h>
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the extra restrictions that __volatile provides on the __asm statements.
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ucom but doesn't set any custom callbacks.
John Long has a HPx9G+ device that requires this.
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generation x1 carbon that have done away with regular F1-F12 keys
from rivo nurges <rix at estpak.ee> and reportedly tested on x1
carbon, x220, and x61s
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(egads!). While there, remove leftover instructions from an early flavour of
tlb_update_indexed(), which crept in by accident.
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on strict alignment archs.
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address in it like the one in mpi too.
shrinks load_xs a bit
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scsi_tasks are still backed by workq, and i dont like having to allocate
storage to defer work.
sas events that cause hotplug events are queued in the softc to be
handled by a single task that loops on the queue for work. think
levelled interrupts. this has a side effect that interrupts are
necessary to enumerate devices for attachment.
i wrote this toward the end of last year, but thought it best to
wait for 5.5 unlock.
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apart from the flags handling in sgls, this shrinks the io hot path
on sparc64 and powerpc a lot. its pretty much the same on
i386/amd64/alpha.
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memory. that means you cant do 8 byte loads and stores on the sg_addr
member cos it wont be 8 byte aligned half the time which makes
strict alignment archs (ie, the fun ones ones) upset.
annotate the sge as being 4 byte aligned. replace the sg_addr member
with sg_addr_lo and sg_addr_hi.
replace htole64 assignment of the sg addr with a wrapper that does
the right thing with a couple of htolem32 calls.
generated code shrinks again.
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included there
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on behalf of all its callers.
use htolem32 and lemtoh32 to handle the message context.
both save bytes.
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requires and the driver provides. without this gcc assumes the
alignment of these structures is 1, which leads to some horrible
asm.
this is particularly interesting when reading stuff from the
myx_status struct (like the txdone count) which needs to be atomic.
doing byte reads and shifting them into a word in registers isnt
atomic. its also probably a bit slow. specifying the alignment fixes
this.
deraadt@ warned me about this maybe 8 years ago.
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struct xucred becomes the structure for syscalls (mount(2) and nfssvc(2)).
ok deraadt@ beck@
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has these enabled and this leads to memory corruption that (surprisingly)
only shows up when running PIE.
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report IDs, on those cases some positions on sc_subdevs[] can be null.
Initial analysis by guenther@.
ok mpi@
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revision.
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testing help mpi@
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affecting R4000 processors revision 2.x and below (found on most R4000 Indigo
and a few R4000 Indy).
Since this errata gets triggered by TLB misses when the code flow crosses a
page boundary, this code attempts to identify code pages prone to trigger the
errata, and force the next page to be mapped for at least as long as the
current pc lies in the troublesome page, by creating wiring extra TLB entries.
These entries get recycled in a lazy-but-aggressive-enough way, either because
of context switches, or because of further tlb exceptions reaching trap().
The errata workaround code is only compiled on R4000-capable kernels (i.e.
sgi GENERIC-IP22 and nothing else), and only enabled on affected processors
(i.e. not on R4000 revision 3, or on R4400).
There is still room for improvemnt in unlucky cases, but in this simple enough
incarnation, this allows my R4000 2.2 Indigo to finally reliably boot multiuser,
even though both /sbin/init and /bin/sh contain code pages which can trigger
the errata.
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and which bits end up in the actual tlb registers.
On non-R8000 kernels, shrink the actual physical address bits to add a new
software bit, PG_SP (for `special'), which will be used shortly. This halves
the physical memory addressable by non-MIPS_PTE64 kernels, which should not
be a problem anyway.
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