summaryrefslogtreecommitdiff
path: root/sys
AgeCommit message (Expand)Author
2020-12-25expose the mcx timer as a timecounter.David Gwynne
2020-12-25match on Gemini Lake I2CJonathan Gray
2020-12-25Refactor klist insertion and removalVisa Hankala
2020-12-25Small smr_grace_wait() optimizationVisa Hankala
2020-12-24Do proper accounting of zero length TDs. Currently a specific numberMarcus Glocker
2020-12-24Extract clock frequency from _DSD properties.Patrick Wildt
2020-12-24Implement capability register overrides based on _DSD properties.Mark Kettenis
2020-12-24regenJonathan Gray
2020-12-24add some NVMe devices and Intel Comet Lake host bridgesJonathan Gray
2020-12-24Initialize mips64 pmap pool using IPL_VM.Visa Hankala
2020-12-24ramdisks do not contain WOLTheo de Raadt
2020-12-24handle reported core clock frequency of 0 on newer Intel Comet LakeJonathan Gray
2020-12-24tsleep(9): add global "nowake" channel for threads avoiding wakeup(9)cheloha
2020-12-24Add Wake on LAN support to rge(4).Kevin Lo
2020-12-23sigsuspend(2): change wmesg from "pause" to "sigsusp"cheloha
2020-12-23nanosleep(2): shorten wmesg from "nanosleep" to "nanoslp"cheloha
2020-12-23Use IPL_VM for the pmap pool like we do on amd64.Mark Kettenis
2020-12-23Ensure that filt_dead() takes effectVisa Hankala
2020-12-23Clear error before each iteration in kqueue_scan()Visa Hankala
2020-12-23Fix regulators that use "active-low" polarity. Our implementation nowMark Kettenis
2020-12-23Handle a few more userland traps that would lead to a kernel panic.Mark Kettenis
2020-12-22have the ifrxr info stuff report the buffer size the hw handles.David Gwynne
2020-12-22Use SIGILL for the Facility Unavailable Interrupt in usermode.gkoehler
2020-12-22Add PCIe clocks.Mark Kettenis
2020-12-22For a while the kerrnel reports EACCES to userland if pf blocks aAlexander Bluhm
2020-12-22Implement select(2) and pselect(2) on top of kqueue.Martin Pieuchot
2020-12-22Defer hardware initialization in order to give things like PCIe PHYsMark Kettenis
2020-12-22Clear FSCR register. This gives us a sane default state where all facilitiesMark Kettenis
2020-12-22name the rx rings like ix does for systat mbDavid Gwynne
2020-12-22Make clang the default compiler on loongson.Visa Hankala
2020-12-22stop showing amd l3 cache informationJonathan Gray
2020-12-21Only enable rasops1_putchar8() and rasops1_putchar16() optomizations onMark Kettenis
2020-12-20Accept reject and blackhole routes for IPsec PMTU discovery.Alexander Bluhm
2020-12-20Fix typo.Mark Kettenis
2020-12-20The TCE table needs to be aligned on a boundary that is a multiple of itsMark Kettenis
2020-12-20Introduce klistopsVisa Hankala
2020-12-20Convert uvm_km_valloc(9) calls to km_alloc(9). Tested in qemu withJonathan Matthew
2020-12-20sync with i915_pciids.hJonathan Gray
2020-12-20drm/i915: Remove dubious Valleyview PCI IDsJonathan Gray
2020-12-20remove duplicate device id caused by subids in INTEL_IVB_Q_IDSJonathan Gray
2020-12-20test against [VM_MIN_ADDRESS, VM_MAXUSER_ADDRESS] in access_ok()Jonathan Gray
2020-12-19Apply r1.86 of amd64 acpi_machdep.c to arm64 and i386, converting a fewJonathan Matthew
2020-12-19There's no need to include the OFW GPIO header.Patrick Wildt
2020-12-19Add support for the i.MX8MP PCIe clocks.Patrick Wildt
2020-12-18Add support for the i.MX8MP second ethernet. The Plus SoC not only has thePatrick Wildt
2020-12-18Emulate open drain GPIOs. This replaces the hack added in the last commit.Mark Kettenis
2020-12-18Add symbolic constants related to open source and open drain GPIOs.Mark Kettenis
2020-12-18Make large read and write transactions work.Mark Kettenis
2020-12-18Add glue for the USB3 controller on the i.MX8MP SoC. NXP had this glue forPatrick Wildt
2020-12-18Add code to initialize the USB 3 PHY on i.MX8MP.Patrick Wildt