| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-04-05 | Add more initialization code such that things work with the EDK2-based | Mark Kettenis | |
| UEFI firmware as well. | |||
| 2018-04-05 | Zap the obsolete PF_TRANS_ALTQ. | Lawrence Teo | |
| Note: Remember to "make includes" and recompile the following programs together with the kernel: sbin/pfctl usr.sbin/authpf usr.sbin/ftp-proxy usr.sbin/relayd usr.sbin/tftp-proxy Thanks to sthen@ for checking the ports tree. ok bluhm@ sashan@ visa@ | |||
| 2018-04-05 | Explicitly check PF_TRANS_RULESET in DIOCXBEGIN, DIOCXCOMMIT, and DIOCXROLLBACK. | Lawrence Teo | |
| ok bluhm@ sashan@ visa@ | |||
| 2018-04-05 | typo in printf - was _PRO, should be _PR0 | Mike Larkin | |
| ok kettenis | |||
| 2018-04-03 | regen | Mark Kettenis | |
| 2018-04-03 | Add Marvell ARMADA 7K/8K (CP110) Root Complex. | Mark Kettenis | |
| 2018-04-03 | Match on the more specific "marvell,armada8k-pcie" instead of the generic | Mark Kettenis | |
| "snps,dw-pcie" for now. There are considerable variations between implementations of the Synapsys Designware PCIe core and glue logic and the current code isn't flexible enough to deal with that yet. | |||
| 2018-04-03 | Move FREF()s just after fd_getfile() in sys_kevent(), sys_lseek() and | Martin Pieuchot | |
| getvnode(). ok millert@ | |||
| 2018-04-03 | Add proper FREF()/FRELE() dance in sys_fchdir(). | Martin Pieuchot | |
| The syscall doesn't sleep before a vnode reference is taken, so it doesn't stickly need the refcounts now. But they will be soon be used for parrallelism, so make it ready. ok bluhm@ | |||
| 2018-04-03 | Call FREF() right after fd_getfile() in dodup3(). | Martin Pieuchot | |
| ok millert@, bluhm@ | |||
| 2018-04-03 | Silence assertwaitok() if we are in ddb(4). | Martin Pieuchot | |
| ok bluhm@ | |||
| 2018-04-03 | Deactivate witness(4) checks if we are in ddb(4), when `db_active' is set. | Martin Pieuchot | |
| Prevents witness(4) from panic'ing the kernel now that mutexes and rwlock are always "taken" while in ddb(4). ok visa@ | |||
| 2018-04-03 | remove a 15-year old #if 0 | Mike Larkin | |
| 2018-04-03 | use link0 to use llprio in transmitted packets, regardless of mbuf prio. | David Gwynne | |
| some ISPs now provide services over vlans, but require vlan packets going to the internet have their priority set to 1 (ie, 0 on the wire) or they will be dropped. configuring this on openbsd requires config in several places, eg, pf rules to set the prio on ip packets, llprio on the pppoe interface for it's management frames, and the llprio on the vlan interface if you're using dhclient on it. this has the side effect that you can no longer use priority queuing, and can be error prone to get right. using link0 to flatteng the priority for isp transit is simple to configure, and allows priority queuing. a man page update is coming. ok henning@ | |||
| 2018-04-02 | Enable mvrng(4). | Mark Kettenis | |
| 2018-04-02 | Add mvrng(4), a driver for the random number generator on the Marvell Armada | Mark Kettenis | |
| 7K & 8K SoCs. | |||
| 2018-04-02 | Attach fec(4) to i.MX8M as well. | Patrick Wildt | |
| 2018-04-02 | Attach imxiomuxc(4) to i.MX8M as well. | Patrick Wildt | |
| 2018-04-02 | Enable imxiomuxc(4). | Patrick Wildt | |
| 2018-04-02 | Move imxiomuxc(4) to sys/dev/fdt. | Patrick Wildt | |
| 2018-04-02 | Move the code that sets the correct SATA phy settings into imxahc(4) | Patrick Wildt | |
| by making use of the iomuxc regmap. While there I realized that the naming definitions for the first two bits of the register are wrong. Thus, update the mask to include all lower bits and rename bit 1 to denote "MPLL enable". This should be flipped last to turn it on. ok kettenis@ | |||
| 2018-04-02 | Implement a regmap lookup by compatible since unfortunately not all | Patrick Wildt | |
| regmaps are referenced by nodes or phandles. ok kettenis@ | |||
| 2018-04-02 | Enable fec(4). | Patrick Wildt | |
| 2018-04-02 | Move fec(4) to sys/dev/fdt. | Patrick Wildt | |
| 2018-04-02 | Enable imxccm(4). | Patrick Wildt | |
| 2018-04-02 | Move imxccm(4) to sys/dev/fdt. | Patrick Wildt | |
| 2018-04-02 | Add dwpcie(4), a (minimal) driver for the Synopsys Designware PCIe core in | Mark Kettenis | |
| Root Complex mode. In its current state it probably only works on the Marvell Armada 7K and 8K SoCs, but the same core is used on many other cores as well. | |||
| 2018-04-02 | Have fec(4) make use of the clock framework by implementing the enet | Patrick Wildt | |
| ref clock in imxccm(4). We can now also remove the global variable that stored the pointer to the imxccm(4) softc. | |||
| 2018-04-02 | No need to include imxccmvar.h anymore. | Patrick Wildt | |
| 2018-04-02 | Have imxahci(4) make use of the clock framework by implementing the sata | Patrick Wildt | |
| and sata ref clock in imxccm(4). | |||
| 2018-04-02 | Have imxehci(4) make use of the clock framework by implementing the phy | Patrick Wildt | |
| clock in imxccm(4). ok kettenis@ | |||
| 2018-04-02 | Enable dwpcie(4). | Mark Kettenis | |
| 2018-04-02 | Add dwpcie(4), a (minimal) driver for the Synopsys Designware PCIe core in | Mark Kettenis | |
| Root Complex mode. In its current state it probably only works on the Marvell Armada 7K and 8K SoCs, but the same core is used on many other cores as well. | |||
| 2018-04-02 | Do not add 32 to the "base" SPI number. Apparently the offset of the first | Mark Kettenis | |
| SPI is already included and adding 32 means we skip the first 32 available MSI vectors, which is quite disastous if we only have 32 vectors like on the Marvell Armada 8040. ok patrick@ | |||
| 2018-04-02 | Add size to free() | David Hill | |
| OK millert@ visa@ | |||
| 2018-04-02 | Use memcpy on freshly allocated memory and add the free size. | David Hill | |
| OK millert@ | |||
| 2018-04-02 | Pay attention to the "reg-io-width" and "reg-shift" properties and avoid | Mark Kettenis | |
| using the "a4x" bus tag for the non-console code in the fdt glue. ok patrick@ | |||
| 2018-04-02 | Remove I2C iomux descriptions from the time before we set those up | Patrick Wildt | |
| using the device tree. | |||
| 2018-04-02 | enable snooping on Intel Apollo Lake HD Audio, pt out & ok jsg | Henning Brauer | |
| 2018-04-02 | attach on Intel Apollo Lake SMBus, ok jsg | Henning Brauer | |
| 2018-04-02 | regen | Henning Brauer | |
| 2018-04-02 | add a bunch of Intel Apollo Lake devices found on NUC6CAYH / Celeron J3455 | Henning Brauer | |
| input & ok jsg | |||
| 2018-04-02 | Add support for register shift/io-width. This allows us to support UARTs | Mark Kettenis | |
| that are mostly NS16550 compatible but use 32-bit instead of 8-bit registers such as the Synopsys Designware UARTs found on many armv7, arm64 and amd64 SoCs. tested by florian@, blum@ ok deraadt@ | |||
| 2018-04-01 | Pull out the regmap lookup from the switch. This way we can still | Patrick Wildt | |
| enable the PLL even if the (optional) "fsl,anatop" property is not available or if the regmap cannot be found. Suggested by kettenis@ | |||
| 2018-04-01 | Disable the USB charging detection using a regmap instead of cross- | Patrick Wildt | |
| calling imxccm using a special function. ok kettenis@ | |||
| 2018-04-01 | Enable imxanatop(4) on RAMDISK as well so we can use it to disable | Patrick Wildt | |
| the USB charging detect so that we can replace the current code in imxccm(4). | |||
| 2018-04-01 | Stop using a global softc variable in most functions that are called | Patrick Wildt | |
| from the clock framework, and instead always pass the driver's softc as function parameter. | |||
| 2018-04-01 | Retrieve AHB clock from clock framework. | Patrick Wildt | |
| 2018-04-01 | Remove unfinished PCIe support from imxccm(4). We can do better than | Patrick Wildt | |
| that when we tackle it again. | |||
| 2018-04-01 | In an attempt to OFW-ify fec(4) it turns out that the MII speed | Patrick Wildt | |
| has currently not been set correctly. The phy speed is based on IPG clock, not the Ethernet PLL divisor. Also when we bumped the frequency base from kHz to Hz, we missed to update the divisor as well. Clarify the formula being used to calculate the phy speed and make use of the clock framework. ok kettenis@ | |||
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